Mitsubishi Denki Kabushiki Kaisha

Renesas Technology Corp.

Mitsubishi Electric Engineering Company, Limited

Mikio Asakura

Hideto Hidaka

Tsukasa Ooishi

Kiyohiro Furutani

Kazuyasu Fujishima

Kazutami Arimoto

Shigeki Tomishima

Yoshio Matsuda

Masaki Tsukude

Tadaaki Yamauchi

Kyoji Yamasaki

Tetsuo Kato

Takeshi Hamamoto

Kenichi Yasuda

Kei Hamade

Tetsushi Tanizaki

Takashi Ito

Koji Tanaka

Yasuhiko Tsukikawa

Takaharu Tsuji

Kengo Aritomi

Katsumi Dosaka

Takashi Kono

Takashi Itou

Masanori Hayashikoshi

Tomoya Kawagoe

Yuichiro Komiya

Yoshito Nakaoka

Takuya Ariki

Takayuki Nishiyama

Fukashi Morishita

Seiji Sawada

Takeo Miki

Takayuki Miyamoto

Satoshi Kawasaki

Shinji Kawai

Yasuhiro Matsumoto

Yukiko Maruyama

Yasuhiko Okasaka

Masaaki Ura

Shinji Tanaka

Yasuhiro Konishi

Katsuhiro Suma

Kouji Tanaka

Shigeru Kikuda

Masakazu Hirose

Kenji Tokami

Jun Nakai

Kazuhiko Takami

Tetsuo Katoh

Shigekazu Aoki

Osamu Kometani

Shoichi Wakano

Kiyoomi Oshigoe

In a semiconductor memory unit to which a plurality of different functions can be imparted by merely changing a portion of its production process, the improvement comprises: a plurality of data buses which include first data buses for use only in one of the functions and the remaining data buses for use in the one and the remainder of the functions; wherein when the semiconductor memory unit performs the remainder of the functions, the first data buses are utilized for the semiconductor memory unit.

Semiconductor memory unit

Drains of first and second transistors are connected to a low level line of an internal circuitry such as a sense amplifier related to determination of a potential in a memory cell. The first transistor has its gate diode-connected to a sense drive line and its source grounded. The second transistor receives at its gate an internally generated signal, and its source is grounded. In the standby state, the potential of the sense drive line is set higher than low level of said word lines by the threshold voltage Vthn of the first transistor and used as dummy GND potential Vss', and in the active state, the second transistor is rendered conductive so as to prevent floating of the sense drive line from the dummy GND potential Vss&#x2032;.

Semiconductor memory device capable of overcoming refresh disturb

A semiconductor memory device includes a command decoder receiving an external signal and issuing a command, a clock buffer receiving an external clock, gates and a refresh counter. When a test signal is at L-level, an auto-refresh signal is issued in accordance with the output of the command decoder. When the test signal is at H-level, the auto-refresh signal is issued in accordance with the output (external clock) of the clock buffer. Thereby, the test can be performed with a good timing accuracy even by a low-speed tester.

Semiconductor memory device having a circuit for fast operation

A tester is connected to a signal output terminal provided in a DRAM chip, and a frequency of a clock signal output from an internal timer is monitored. The frequency of the clock signal is varied by changing the combination of 3 bit signals, so as to obtain signals by which the frequency closest to the set value is obtained. A fuse in the internal timer is disconnected to set the frequency of the clock signal so as to obtain the same state as in the case where that signal is applied. The internal timer includes an oscillator formed of a plurality of inverters connected in ring shape and a variable capacitance circuit for each inverter. Each variable capacitance circuit includes a plurality of sets of transfer gates, fuses and capacitors connected between the output node of the corresponding inverter and a prescribed potential line.

Ring oscillator having variable capacitance circuits for frequency adjustment

In response to an output data width switching mode signal, a predecoder zone&plus;selector zone outputs selection signals SEL to SEL and WORDA to WORDC to a preamplifier&plus;write driver zone. The preamplifier&plus;write driver zone can switch connection between global I/O lines GIO< > to GIO< > and a data bus in response to these selection signals. Read data is output to a pad without through a selector circuit or the like on the data bus, whereby a simple structure can be obtained with no critical adjustment of a delay time resulting from mode switching or address change.

Semiconductor memory device capable of switching output data width

A test signal generating circuit generates internal test control signals from a small number of signals supplied via an address terminal in a test mode operation. According to the test control signals, the values of internal row address signal bits from an address buffer are set, while a row-related control circuit with test control function controls operations of a row selection circuit and bit line peripheral circuitry according to the test control signals. A plurality of word lines are driven simultaneously into a selected state and an acceleration test is performed according to a small number of control signals in a short period of time. Voltage stress applied between memory cell capacitors and between word lines can be accelerated with a small number of control signals.

Semiconductor memory device capable of correctly and surely effecting voltage stress acceleration

A semiconductor memory device includes a plurality of array blocks including word lines, memory cells, bit lines, dummy word lines and transistors. In a test mode, rather than a word line a dummy word line is selected. Selectively turning on either one of the transistors allows a bit line connected thereto to be driven to a ground potential. Thus, a channel leak can be detected. In a mode other than the test mode, a defective word line is substituted by a spare word line included in a spare block.

Semiconductor memory device with memory test circuit

A semiconductor memory device includes: a memory cell region constructed of blocks and a memory cell region constructed of blocks. The blocks and the blocks are continuously disposed. A block decoder outputs block select signals to the respective blocks. As a result, power consumption of the semiconductor memory device is reduced.

Semiconductor memory device with low power consumption

Complementary sub-decode signals to be provided to a sub-word line driver are separately generated through different circuits using individual power-supply voltages. Thus, the generation of a through current in the sub-word line driver is prevented.

Semiconductor memory device with a hierarchical word line configuration capable of preventing leakage current in a sub-word line driver

Pads are alignedly arranged in a central region of a semiconductor chip and are also arranged at an outer peripheral portion of the central portion of the chip. A pad at the outer peripheral portion is electrically connected to a die pad mounting the chip thereon with an insulative material interposed therebetween. A potential supplied to the pad positioned at the outer peripheral portion can be stabilized by parasitic capacitance of the die pad, and a potential of the die pad can be externally monitored easily by removing away a portion of mold resin after resin sealing. Further, due to a cress shaped arrangement of the pads, a voltage down converter can be arranged in line with the pads and at outer periphery of the chip without area penalty. In testing operation, a switching circuit switches a function of a pad to another pad so that cross-shapedly arranged pads are equivalently arranged in a line.

Semiconductor device with efficiently arranged pads

Drains of first and second transistors are connected to a low level line of an internal circuitry such as a sense amplifier related to determination of a potential in a memory cell. The first transistor has its gate diode-connected to a sense drive line and its source grounded. The second transistor receives at its gate an internally generated signal, and its source is grounded. In the standby state, the potential of the sense drive line is set higher than low level of said word lines by the threshold voltage Vthn of the first transistor and used as dummy GND potential Vss&prime;, and in the active state, the second transistor is rendered conductive so as to prevent floating of the sense drive line from the dummy GND potential Vss&prime;.

Semiconductor memory device

A semiconductor memory device comprises a DRAM memory cell array comprising a plurality of dynamic type memory cells arranged in a plurality of rows and columns, and an SRAM memory cell array comprising static type memory cells arranged in a plurality of rows and columns. The DRAM memory cell array is divided into a plurality of blocks each comprising a plurality of columns. The SRAM memory cell array is divided into a plurality of blocks each comprising a plurality of columns, corresponding to the plurality of blocks in the DRAM memory cell array. The SRAM memory cell array is used as a cache memory. At the time of cache hit, data is accessed to the SRAM memory cell array. At the time of cache miss, data is accessed to the DRAM memory cell array. On this occasion, data corresponding to one row in each of the blocks in the DRAM memory cell array is transferred to one row in the corresponding block in the SRAM memory cell array.

Semiconductor memory device for simple cache system

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Hyogo, Japan

Mikio Asakura