Kabushiki Kaisha Toshiba

Toshiba Memory Corporation

Kioxia Corporation

Asahi Kasei Kabushiki Kaisha

Toshiba Memeory Corporation

Asahi Kasei Chemicals Corporation

Mikihiko Ito

Masaru Koyanagi

Fumiya Watanabe

Kazushige Kawasaki

Yasuhiro Hirashima

Kei Shiraishi

Satoshi Tsukiyama

Masahiro Yoshihara

Shinya Okuno

Shigeki Nagasaka

Masafumi Nakatani

Akira Umezawa

Katsuki Matsudera

Maya Inagaki

Noriko Yamauchi

Hiroshi Maejima

Satoshi Inoue

Satoru Takase

Chikaaki Kodama

Masami Masuda

Kensuke Yamamoto

Takahiko Hara

Kazuyuki Hamada

Yutaka Shimizu

Shouichi Ozaki

Tohru Kimura

Takashi Taira

Yumi Takada

Shintaro Hayashi

Mutsumi Maeda

Taichi Wakui

Masaaki Kondoh

In a semiconductor integrated circuit, an input circuit includes an input and an output stage electrically connected to the input stage via a first node and a second node. The input stage includes a first transistor, a second transistor, a third transistor, a fourth transistor, a first time constant adjusting circuit, and a second time constant adjusting circuit. The first transistor includes a gate that receives an input signal. The second transistor includes a gate that receives a reference signal. The third transistor is disposed adjacent to a drain of the first transistor. The fourth transistor is disposed adjacent to a drain of the second transistor. The first time constant adjusting circuit is electrically connected between a gate of the third transistor and the first node. The second time constant adjusting circuit is electrically connected between a gate of the fourth transistor and the second node.

Semiconductor integrated circuit and semiconductor storage device

According to one embodiment, a memory device includes: a first chip including a first circuit, first and second terminals; a second chip including a second circuit and a third terminal; and an interface chip including first and second voltage generators. The first chip is between the second chip and the interface chip. The first terminal is connected between the first circuit and the first voltage generator. A third end of the second terminal is connected to the third terminal and a fourth end of the second terminal is connected to the second voltage generator. A fifth end of the third terminal is connected to the second circuit and a sixth end of the third terminal is connected to the second voltage generator via the second terminal. The third end overlaps with the sixth end, without overlapping with the fourth end.

Memory device

A semiconductor device comprises an input circuit that includes a first comparator configured to output a first output signal and a second output signal having a phase opposite to that of the first output signal, based on a comparison result of a first input signal and a second input signal which is a complementary signal of the first input signal. A duty ratio of the first output signal and a duty ratio of the second output signal are different from a duty ratio of the first input signal and a duty ratio of the second input signal, respectively.

Semiconductor device

A semiconductor memory device includes a differential waveform shaping circuit including first and waveform shaping circuits connected in parallel. The first waveform shaping circuit has a first inverting amplifier, and two inverters connected in series. The first inverting amplifier inverts and differentially amplifies an input signal having a rectangular waveform. Then, the output of the first inverting amplifier is passed through the two inverters. The second waveform shaping circuit has a first inverter, a second inverting amplifier, and a second inverter connected in series. The second inverting amplifier inverts and differentially amplifies the output signal from the first invertor, and the second inverter inverts the output signal from the second inverting amplifier. The differential waveform shaping circuit generates an output signal by averaging the output signal from the first waveform shaping circuit and the output signal from the second waveform shaping circuit.

Semiconductor memory device

According to one embodiment, a memory device includes: a first chip including a first circuit, first and second terminal; a second chip including a second circuit and a third terminal; and an interface chip including first and second voltage generators. The first chip is between the second chip and the interface chip. The first terminal is connected between the first circuit and the first voltage generator. A third end of the second terminal is connected to the third terminal and a fourth end of the second terminal is connected to the second voltage generator. A fifth end of the third terminal is connected to the second circuit and a sixth end of the third terminal is connected to the second voltage generator via the second terminal. The third end overlaps with the sixth end, without overlapping with the fourth end.

Memory device with a plurality of stacked memory core chips

A semiconductor device includes a base member and semiconductor chips stacked on the base member. The semiconductor chips include a first semiconductor chip and a second semiconductor chip adjacent to the first semiconductor chip. The first semiconductor chip includes a semiconductor substrate, a functional layer and through electrodes. The through electrodes extend from the back surface to the front surface of the semiconductor substrate, and are electrically connected to the functional layer on the front surface. The second semiconductor chip is electrically connected to the first semiconductor chip through connection members connected to the through electrodes. The functional layer includes first and second contact pads. The second contact pad is positioned at a level between the semiconductor substrate and the first contact pad. The through electrodes include a first through electrode connected to the first contact pad and a second through electrode connected to the second contact pad.

A semiconductor device includes a base member, a stacked body on the base member, a first conductor on the stacked body, a second conductor on a top surface of the base member, and a connection conductor connecting the first conductor and the second conductor. The stacked body includes semiconductor chips stacked and a shared terminal connected to the plurality of semiconductor chips. The plurality of semiconductor chips each includes a functional element on a front surface side thereof and a through electrode extending from a back surface to the front surface side. The shared terminal has a top end positioned at a top surface of the stacked body and a bottom end positioned at a bottom surface of the stacked body. The first conductor is connected to the top end of the shared terminal, and the second conductor is electrically connected to the bottom end of the shared terminal.

A semiconductor memory device includes a first transistor including a first end connected to a first pad and a second end connected to a first node, a second transistor including a first end connected to a second pad and a second end connected to the first node, a third transistor including a first end connected to the second pad, a second end connected to the first node, and a gate connected to a second node and having a size different from that of the second transistor, a fourth transistor including a first end connected to the first pad, a second end connected to the second node, and a gate connected to the first node, and a fifth transistor including a first end connected to the second pad, a second end connected to the second node, and a gate connected to the first node.

A semiconductor device includes first input/output circuits for a first channel, first input/output pads corresponding to the first input/output circuits, respectively, wherein the first input/output pads are aligned along and extends in a first direction, second input/output circuits for the first channel, second input/output pads corresponding to the second input/output circuits, respectively, wherein the second input/output pads are aligned along and extends in a second direction, and an input circuit between the first input/output pads and the second input/output pads, and connected to a memory to which the input circuit inputs data from the first input/output circuits and the second input/output circuits. The input circuit is positioned such that a first line extending perpendicular to the first direction from one of the first input/output pads and a second line extending perpendicular to the second direction from one of the second input/output pads intersect a portion of the input circuit.

According to one embodiment, there is provided a storage device including a control chip and a plurality of memory chips. The control chip has an input buffer common to the control chip and the plurality of memory chips and electrically connected to an external terminal. A first transmission path going through the input buffer and a second transmission path not going through the input buffer are provided between the external terminal and the plurality of memory chips. In a first mode, the control chip enables the input buffer so as to activate the first transmission path and, in a second mode, disables the input buffer so as to activate the second transmission path.

Storage device

A semiconductor device includes a first chip having a through via, a second chip having a first terminal that is electrically connected to the through via, and a substrate having a second terminal disposed on a first surface thereof and electrically connected to the first terminal. When viewed along a straight line that intersects a center axis that is perpendicular to the first surface and intersects a center point of the substrate, the first terminal is disposed further towards the center axis than the second terminal and the through via is disposed further towards the center axis than the first terminal.

According to one embodiment, a semiconductor amplifier circuit includes: a first amplifier circuit including first and second P-type transistors; a second amplifier circuit including first and second N-type transistors; and first to seventh current mirror circuits. The first and second current mirror circuits are connected to drains of the first and second P-type transistors. The third and fourth current mirror circuits are connected to drains of the first and second N-type transistors. The sixth current mirror circuit is connected to the first, fourth and fifth current mirror circuits. The seventh current mirror circuit is connected to the second, third and fifth current mirror circuits.

Semiconductor amplifier circuit

According to one embodiment, a semiconductor device includes a first semiconductor chip; a first wiring and a second wiring which are provided above a first surface of the first semiconductor chip; a first terminal connected to one end of the first wiring and one end of the second wiring, and connected to an outside; a second terminal connected to the other end of the first wiring; and a third terminal connected to the other end of the second wiring, and connected to the second terminal.

Growing community of inventors

Tokyo, Japan

Mikihiko Ito