At&t Bell Laboratories

Lucent Technologies Inc.

At+t Corp.

Mikiel L Larson

Wing N Toy

Bruce E Briley

John Montsma

Avinash K Vaidya

Douglas A Kimber

John H Pokropinski

Wayne R Wilcox

Brian P Doherty

Gustavus H Zimmermann, Iii

Anne A Robrock

A highly available processor complex that can use industry standard hardware and software through use of an N+K sparing arrangement with a separate monitor ('watchdog') processor. The watchdog processor monitors periodic 'heartbeat' messages from the monitored elements and can change activity and status of such monitored elements through control messages. Further, the watchdog processor is operatively connected to a power control circuit that controls the power to the monitored elements. Thus, the watchdog processor can guarantee that a faulty element can be rendered non-functional and can also totally restart an element through power cycling it.

System for providing automatic power control for highly available n+k

An arbitration circuit that uses a unique history register that is combined with a value representing bus requests to index into a table. All possible combinations of history register requests are stored in the table along with a corresponding grant. A block of the table is selected by the history register, and then the request is used to index into the block to determine which request receives a grant. The grant is then shifted into the history register. Advantageously, more than one table may be stored in memory which can be selected by an arbiter controller.

Dynamically programmable bus arbiter with provisions for historical

A structure connecting superconductor transmission lines to integrated circuits comprises a plurality of interconnection substrates having superconducting transmission path deposited thereon in contact with metallic contact areas, and integrated circuit chip carrier substrates for mounting integrated circuits and having metallic contact areas. The substrates are mounted in a retainer structure and are separated by spacers which have apertures in registration with the contact areas. Contact devices are selectively inserted in the apertures to establish an interconnection pattern between the substrates. The retainer structure applies force to the substrates to assure physical contact between the substrates and the contact device. The structure may be assembled and disassembled for replacement of parts or reconfiguration of interconnections, without the application of heat or other processes which are incompatible with relatively brittle and heat sensitive superconducting materials. The complete structure may be submerged in a bath of liquid nitrogen for cooling. The space provided by the spacers allows for access by the cooling liquid to the superconducting material on the substrates.

Superconductor interconnection apparatus

An electronic system having components operating at low temperature at various locations within the system, cryogenic fluid and electrical power are distributed by means of the same conduit. In one embodiment, the conduit consists of a supply section and a return section with each section comprising a channel for conveying cryogenic fluid having superconducing walls for conveying electrical power. In another embodiment of the invention, the conduit comprises a copper rod having channels formed therein for the transport of cryogenic fluid and a channel for supporting a rod of superconducing material therein. The superconducing rod conducts electrical current to a subsystem while being cooled by cryogenic fluid in nearby channels and the cryogenic fluid is used at its destination for cooling purposes. In yet another embodiment of the invention, cryogenic fluid is transported between a source of cryogen and subsystems using the fluid, by means of a pair of concentric conduits with the walls of each conduit comprising superconducting material for simultaneously providing electrical power to the subsystems employing the cryogenic fluid.

Superconducting bus bar

Apparatus for preventing the unauthorized detection of the start and end of packets being communicated within a packet switching system. The packet switching system comprises a plurality of packet switching networks that are interconnected by trunks. Each switching network has a number of trunk controllers with each terminating one of the trunks interconnecting that network to other networks. Each controller has an encrypting circuit for only encrypting the flag of each packet before the packet is transmitted on the connected trunk and a decrypting circuit for decrypting the flag of each packet received from the connected trunk. The decrypting circuit on the receiving side of a trunk recovers flag synchronization with the encrypting circuit on the transmitting side of the trunk by the exchange of special packets. Each flag comprises a plurality of bytes. The decrypting circuit can automatically adjust for a predefined number of errors in the flag bytes or a predefined number of flag bytes appearing in the data of a packet.

Packet switching architecture providing encryption across packets

Trunk controllers (131) at each end of a trunk (118) of a packet switching system (FIGS. 1A and 1B) include an idle packet generator (1419) and an idle packet detector (1420). During idle periods, when packets are not available for transmission, the transmitter of each idle trunk controller generates and transmits a continuous sequence of flags (801/810) on the trunk. Periodically during the idle periods, the idle packet generator generates and provides to the transmitter (1403) for transmission an idle packet (800). An idle packet is structured like a normal packet. However, it is marked as an idle packet by the packet identification (PID) field (804) and contains pseudo-random bits in the data field (806). The receiver (1402) of the other trunk controller receives the idle code and packets including idle packets, discards the idle code, and sends all packets to the idle packet detector. The detector identifies idle packets by their PID field and discards them--blocks them from propagating further--while allowing other packets to pass therethrough.

Idle period signalling in a packet switching system

A self-routing packet switching network in which packets are communicated through stages of the network in response to self-contained addresses and in which a packet is discarded if a packet cannot be transferred to a subsequent stage of the network within a predefined amount of time. In addition, upon a packet being discarded, a maintenance message is transmitted over a maintenance channel to the processor controlling the network. Each network comprises stages of switching nodes which are responsive to the physical address in a packet to communicate the packet to a designated subsequent node. The nodes provide for variable packet buffering, packet address rotation techniques, and inter-node and intra-node signaling protocols. Each node comprises a timer which commences timing for a predefined amount of time upon receipt of a packet. If the timer times out, the packet is discarded and a maintenance message is transmitted to the processor controlling the network. The maintenance message includes the physical address plus an address identifying the network entry point of the packet. By discarding packets after a predefined amount of time, the problem of a self-routing network locking up is avoided when one switching node within the network fails or is experiencing overload traffic conditions.

Lockup detection and recovery in a packet switching network

A multi-stage packet switching network (100) includes a plurality of packet switching nodes (110) each included in one stage of a sequence of stages (101, 102, 103) of the network. Each node (101-1-x) of a stage (101) is connected to a stage bus (220-1) that indicates to the node 'how manieth' stage in the sequence of stages it is a part of, i.e., where in the sequence of stages that node appears. Each node includes circuitry (450) that responds to the information carried by the associated stage bus to select 'that manieth' most significant bit (504) of the destination field (502) of a received packet (500) as the bit on the basis of whose value the packet is routed at the node. On a circuit pack (200) that includes nodes of a plurality of stages, the first stage bus is connected to a register (250) whose contents are the number of the first stage of the pack in the sequence of stages. Adders (210) interconnect the stage buses of sequential stages and act to increment by one the value carried by each sequential stages' stage bus.

Routing address bit selection in a packet switching network

A traffic load control arrangement for a packet switching system (FIGS. 1A and 1B) uses a circuit (1521) in each trunk controller (131) to determine the call traffic load of the trunk controller. To set up a call path, the central processor (115) of a switch (102) selects a trunk (118) to serve the call and sends a logical channel setup packet (500e) indicating either forced or normal selection to the selected trunk's controller (131). If normal selection is indicated, the selected trunk controller refuses to serve the call and returns a channel setup no-acknowledgement packet (500f) to the central processor if the trunk controller's load exceeds a predetermined level. Otherwise, the trunk controller sets up a channel to serve the call and returns a channel setup acknowledgment packet (500g) to the central processor. In response to the no-acknowledgment packet, the central processor attempts to find another trunk to serve the call. In the case of a toll office (104), if no other trunk can be found and a call setup acknowledgment packet (500n) has not yet been returned by the toll office switch to the preceding switch, the toll office switch returns a call setup no-acknowledgment packet (500o) to the preceding switch. The preceding switch responds to receipt of the no-acknowledgment packet by attempting to find a trunk leading to another switch to serve the call.

Traffic load control arrangement and method for a packet switching system

A packet switching network (100) comprises switching nodes (220-222, 230-232, 240-242, 250-252, 260-262, and 270-272) residing on circuit packs (101-104), that are interconnected by packet signal transmission links (110-119, 140-149, 150-159, and 180-189) carrying multiplexed pulse-width modulated signals (450) each representing three bits. A link (112) incoming to a pack (101) connects to an input port (2821) of a demultiplexer (282), whose output ports (2822-2824) are coupled to packet inputs (2401, 2411, 2421) of three nodes (240-242). The incoming signal stream is demultiplexed into three serial signal substreams. Each substream is transmitted to a node for switching. A link (122) outgoing from a pack (101) connects to an output port (2871) of a multiplexer (287) whose input ports (2872-2874) are coupled to the packet outputs (2703, 2713, 2723) of three nodes (270-272). The three incoming serial signal substreams are multiplexed into a signal stream that is transmitted on the link. For multiplexed signals representing the bits of a single packet, (FIGS. 2a-c), the acknowledgment output (2405) of one node (240) coupled to a demultiplexer (282) is connected to the incoming link (112) and the acknowledgment input (2707, 2717, 2727) of each node (270-272) coupled to a multiplexer (287) is connected directly to the outgoing link (122). For multiplexed signals representing the bits of three packets, (FIGS. 3a-c), acknowledgment outputs (2405, 2415, 2425) of the nodes (240-242) that are coupled to a demultiplexer (282) are coupled through a multiplexer (294) to the incoming link (112). Acknowledgment inputs (2707, 2717, 2727) of the nodes (270-272) that are coupled to a multiplexer (287) are coupled through a demultiplexer (291) to the outgoing link (122). Coupling of a packet and acknowledgment input and output pair to a demultiplexer and a multiplexer is made by a lock (246) which alternately makes one connection while it breaks the other connection. The locks that connect to a multiplexer and demultiplexer pair operate in unison.

Multiplexed interconnection of packet switching node packages

In a voice packet switching network (10), following call path set-up, continuity packets (500a-c) are transmitted between the call originating (100) and destination (101) nodes to check call path continuity. The continuity packets carry time stamps of their (503) and the preceding continuity packet's (504) time of transmission, to permit determination of call path transit delay, and computation of asynchrony between clocks (200) of the two nodes. A call path is considered acceptable if one half the path round trip transit delay does not exceed a predetermined maximum acceptable delay. Subsequently transmitted data packets are discarded if their transit delay exceeds the predetermined maximum acceptable delay. Transit delay of a data packet is computed from originating and terminating node clock readings at the time of transmission and reception of the packet, respectively, adjusted for asynchrony of the two clocks.

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St. Charles, IL, United States of America

Mikiel L Larson