Matsushita Electric Industrial Co., Ltd.

Miki Urano

Takashi Taniguchi

Jiro Miyake

Genichiro Inoue

Tamotsu Nishiyama

Kazuki Ninomiya

Keizo Sumida

Shintaro Tsubata

To provide a signal processor for performing processing in fewer cycles by selecting one of the two different operations in accordance with a flag signal and performing the selected operation without the use of a conditional branch instruction, the signal processor is provided with an instruction decoder, a control selecting circuit, a selecting circuit and an arithmetic unit. The instruction decoder decodes an instruction to output two control signals. The control selecting circuit is connected to the instruction decoder and selects one of the control signals in accordance with a flag signal stored in a flag holding circuit to output the selected signal. The selecting circuit selects one of a plurality of input data in accordance with the control signal outputted by the control selecting circuit and outputs the selected data. The arithmetic unit performs an operation on the data outputted by the selecting circuit.

Signal processor for performing conditional operation

A start signal is generated which selects, from among a plurality of sub-periods resulting from division of one cycle period of an external clock signal and each having a length equivalent to one cycle period of an internal clock signal, a sub-period at a corresponding position to a setup time of an external device. When the start signal is generated after a CPU (central processing unit) issues a transmission request signal, there is made a transition to a transmission state. An address signal to the external device is held until data transmission starts between the CPU and the external device in synchronization with the external clock signal in the transmission state.

Data processor

A plurality of signal processing elements are cascade-connected to form a signal processor having three signal paths. The signal processor is a small-sized device which can be shared by sum-of-products calculation and division. In each signal processing element, first and second shifters and an adder-subtracter are used for performing shift addition for multiplication of a variable by a constant which is a basis of the sum-of-products calculation. The adder-subtracter and a third shifter for shifting a result obtained by the adder-subtracter are used for performing subtraction and shifting for obtaining a partial quotient and a partial remainder of division. The partial quotient thus obtained is transferred to the signal processing element in the next stage through a flag holding circuit.

Signal processor

In the case of addition/subtraction of floating-point numbers, two mantissas having their digits aligned in a swapper and in a right shifter are supplied to an adder/subtracter via first and second mantissa selectors and two 1-bit right shifters so that they are subjected to addition/subtraction in the adder/subtracter, the result of which is rounded. In the case of multiplication/division of floating-point numbers, an intermediate sum and a carry, each outputted from a multiplier, are supplied to the above adder/subtracter via the above first and second mantissa selectors and the above two 1-bit right shifters, so that they are added in the adder/subtracter, the result of which is rounded. The result of rounding from the adder/subtracter is outputted as a normalized mantissa through a priority encoder and a left shifter. An exponent is processed by first to third exponent arithmetic units and an exponent selector. Thus, the amount of hardware of an arithmetic apparatus for executing the addition, subtraction, multiplication, and division of floating-point numbers can be reduced.

Arithmetic apparatus for floating-point numbers

A post-processing is executed on a mantissa M and an exponent E of a floating point binary number as a result of subtraction for example, thereby to obtain a mantissa m and an exponent e of the result of the post-processing. Therefore, an output (E-1) of a decrementer and an output (amount of cancelling of mantissa LSA) of an advancing 1 detecting circuit are entered into a minimum value selecting circuit. The minimum value selecting circuit is adapted to set a shift amount SH to (E-1) and a magnitude-relation judging signal CR to 1 when (E-1) is smaller than LSA (that is, when a denormalize processing is required). When (E-1) is not smaller than LSA (that is, when a normalize processing is required), SH is set to LSA and CR is set to 0. A left shifter is adapted to supply, as the mantissa m of the result, a value obtained by executing a left shift processing having a shift amount SH on the mantissa M. A selecting circuit is adapted to supply, as the exponent e of the result, 0 when CR is equal to 1, and an output (E-LSA) of a subtracting circuit when CR is equal to 0. This enables the denormalize processing of a floating point binary number to be executed at a high speed equivalent to that at which a normalize processing is executed.

Method of and apparatus for normalization of a floating point binary

At a format conversion of a floating point number from double-precision to single-precision, a temporary exponent e.sub.1 is obtained by subtracting a double-precision bias B.sub.d from an exponent E of an operand and by adding a single-precision bias B.sub.s thereto. A mantissa M of the operand is shifted to right by a number obtained by adding 1 to an absolute value of the exponent e.sub.1 when e.sub.1 .ltoreq.0. When e.sub.1 &gt;0, the mantissa M is not shifted. the result is rounded to a 23-bit length. When no carry is caused, the rounded value and 0 (when e.sub.1 .ltoreq.0) or e.sub.1 (when e.sub.1 &gt;0) are respectively a mantissa and an exponent to be obtained. The rounded value and e.sub.1 +1 are regarded as a conversion result when e.sub.1 =0 and a carry is caused. A value obtained by shifting the rounded value to right by 1 bit and e.sub.1 +1 are selected when e.sub.1 &gt;0 and a carry is caused. Accordingly, denormalization is executed with a high speed without interrupting a procedure being executed, and conversion results can be always obtained with a minimum number of procedures.

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Miki Urano