Fujitsu Corporation

Miki Takagi

Hiroji Takeyama

Terunobu Maruyama

Takeo Nakamura

Hiroshi Ikeda

Noriyuki Ito

Yoshiyuki Kato

Hiroyuki Sugiyama

Ryoichi Yamashita

Tomoyuki Isomura

Yasunori Abe

Naomi Bizen

Koichi Itaya

Tadashi Konno

Takehiro Yamazaki

Mitsuru Yasuda

Mitsuru Satou

Yuki Kumon

Kazuhiro Matsuzaki

Junko Taira

Hiroshi Noguchi

A design data merging apparatus includes a merging determining unit that determines, for a plurality of design data of which each has product name information and has a same identifier for uniquely identifying a product, whether the product name information given to the plurality of design data are the same, and a merged data creating unit that merges the plurality of design data when it is determined by the merging determining unit that the product name information given to the plurality of design data are the same, and creates merged data obtained by merging a plurality of design data.

Design data merging apparatus and design data merging method

The time and trouble of a mismatch cause analysis after logical equivalence verification can be reduced, and design and verification TAT can be shortened. A logical equivalence verifying device performs logical equivalence verification between two circuits, and displays the result of the logical equivalence verification. A preprocessing sectionperforms structural matching so as to determine whether there are portions corresponding in circuit structure to each other in corresponding logic cones of the two circuits. An internal DBrecords the results of the structural matching as an identifier for each element. A subcone extracting sectionextracts, as a subcone, a collection of elements, which are mutually to one another and have the same identifier, from each logic cone. A verifying sectionperforms logical equivalence verification between the two circuits for each of the extracted subcones. A display control sectiondisplays only those subcones for which the logical equivalence verification has resulted in mismatch.

Logical equivalence verifying device, method, and computer-readable medium thereof

Logical equivalence verifying device, method and computer readable medium thereof

A method for verifying a logical equivalency between two logic circuits having different combinational logic circuits includes the steps of converting into a logic circuit a logic cone that has been determined for each of the two logic circuits, the logic cone including all inputs and all logic circuits which affect one output of the combinational logic circuit, storing a logical expression converted by the converting step and a logic circuit element included in the logic cone while correlating the logical expression with the logic circuit element, and specifying the logic circuit element corresponding to a specified term in the logical expression that has been converted.

Method and apparatus for verifying logical equivalency between logic circuits

A circuit designing apparatus includes a circuit information database to store information regarding a circuit, an automatic designing processing section to read out the information regarding the circuit from the circuit information database and designing the circuit for each predetermined unit to be processed, and a design information database to store design information obtained by the automatic designing processing section and including peculiarizing information of circuit elements, change history information representative of a history of changes of the circuit and terminal load and driving capacity information of the circuit. The circuit designing apparatus allows a desired circuit to be automatically produced, regenerated or optimized.

Circuit designing apparatus, circuit designing method and timing distribution apparatus

A circuit designing apparatus of an interactive type which enables a simplified and highspeed circuit design process while largely reducing a burden on a designer, having a speed analyzing unit for conducting a delay computation for each wiring path on a circuit to be designed and a display control unit for displaying a result of the delay computation by the speed analyzing unit on a display unit. When the speed analyzing unit conducts a delay computation, a delay value of each logic component forming the circuit that is an object of the design is set and altered according to a dullness of a signal waveform inputted to the logic component. The circuit designing apparatus of an interactive type may be applied to a system for conducting a circuit design of an integrated circuit such as an LSI or the like or a printed circuit board.

Interactive circuit designing apparatus which displays a result of component placement and wire routing from a layout design unit

A circuit designing apparatus of an interactive type which enables a simplified and high-speed circuit design process while largely reducing a burden on a designer, having a speed analyzing unit for conducting a delay computation for each wiring path on a circuit to be designed and a display control unit for displaying a result of the delay computation by the speed analyzing unit on a display unit. When the speed analyzing unit conducts a delay computation, a delay value of each logic component forming the circuit that is an object of the design is set and altered according to a dullness of a signal waveform inputted to the logic component. The circuit designing apparatus of an interactive type may be applied to a system for conducting a circuit design of an integrated circuit such as an LSI or the like or a printed circuit board.

Circuit designing apparatus of an interactive type

Growing community of inventors

Kawasaki, Japan

Miki Takagi