Other

Hitachi, Ltd.

Miki Miyaki

Tadaaki Isobe

Naonobu Sukegawa

Shigeko Hashimoto

Koji Nunogawa

Kohki Uwano

Tsuyoshi Okuyama

Tatsuya Ichiki

Each of processing nodes and switching apparatuses constituting a parallel processor system is provided with data transmitting/receiving apparatuses and The data transmitting/receiving apparatus in response to an instruction from a processor P within its own node, transmits data stored in a transfer data buffer to the data transmitting/receiving apparatus of a switching apparatus connected thereto. The data transmitting/receiving apparatus receives data that are transferred, and stores them into a transfer data buffer If any error in receive data is detected by an error detector of the data transmitting/receiving apparatus a retransmission request signal is issued from a retransmission control circuit to the retransmission control circuit of the transmitting apparatus The retransmission control circuit upon receiving the retransmission request signal instructs a data transmission control signal to execute retransmission. The data transmission control circuit causes the buffer control circuit to subtract an established value from a read pointer, and reads out of the transfer data buffer again and retransmits a single frame equivalent of data.

Data transmitting/receiving apparatus for executing data retransmission and parallel processor system

Each of processors in a multiprocessor system has a circuit for sending a synchronizing signal to a storage controller (SC) connected thereto when executing a synchronization instruction such as a start, end or barrier synchronization instruction. Each of the SCs has a circuit for notifying the corresponding processor of establishment of a synchronization upon detection of completion of a check to be made by an address management table FAA and of the issuing of necessary cache cancel requests corresponding to a store instruction issued before the synchronization instruction and upon recognition of the fact that all the processors have sent their synchronizing signals and that the issuing of all the cache cancel requests have been complete.

Parallel processor synchronization and coherency control method and system

Growing community of inventors

Hadano, Japan

Miki Miyaki