Nxp Usa, Inc.

Mikhail Yurievich Semenov

Viacheslav Sergeyevich Kalashnikov

Victor Mikhailovich Mikhailov

Denis Borisovich Malashevich

David Russell Tipple

Alexander Ivanovich Kornilov

Anis Mahmoud Jarrar

Vasily Vladimirovich Korolev

Sergei Victorovich Somov

Synchronizer circuits having controllable metastability are provided, one of which includes: a first flip-flop circuit comprising a first master latch connected in series with a first slave latch; and a second flip-flop circuit comprising a second master latch connected in series with a second slave latch, wherein an output of the first flip-flop circuit is connected to an input of the second flip-flop circuit, at least a portion of the first flip-flop circuit is implemented in a first PWell isolated by an underlying a deep isolation NWell, at least a portion of the first flip-flop circuit is implemented in a first NWell that electrically contacts the deep isolation NWell, the first NWell is connected to a first bias voltage that is less than a positive power supply voltage, and the first PWell is connected to a second bias voltage that is greater than a negative power supply voltage.

Synchronizer with controlled metastability characteristics

An integrated circuit includes a pulse generator having at least one delay circuit with an input that receives a clock signal and an output that provides a delayed clock pulse. The delayed clock pulse has a width proportional to an amount of time required to maintain a magnitude of the clock signal. A pulse latch circuit includes a clock input coupled to receive the delayed clock pulse, a data input coupled to receive a data value, and a data output, wherein the pulse latch circuit outputs and holds the data value at the data output each time the delayed clock pulse is provided at the clock input, and the pulse latch circuit operates on a continuous voltage source that supplies power during power on and power off modes.

Pulsed latch system with state retention and method of operation

An electronic device includes a logic circuit, a pullup acceleration circuit, a first signal propagation path, and a second signal propagation path. The first signal propagation path propagates a logic value transition from an input terminal of the logic circuit to an output terminal of the logic circuit through the input terminal, two inverters of the logic circuit, a switch of the logic circuit, and the output terminal within a first amount of time based on a transition at the first input terminal. The second signal propagation path propagates the logic value transition from the input terminal to the output terminal through one inverter of the logic circuit and the pullup acceleration circuit within a second amount of time. The second amount of time is shorter than the first amount of time in response to the logic circuit being non-monotonic with respect to the logic value.

System and method of acceleration of slow signal propagation paths in a logic circuit

This disclosure describes a library optimization system that creates modified standard cells with reduced leakage currents that meet predefined cell area, timing, and leakage requirements. The library optimization system selects transistors to upsize based upon the fact that transistors of a same type, such as p-channel or n-channel transistors, that are connected in series produce a small reverse bias between the gate and source, known as a stacking effect. The stacking effect results in an inherent decrease in leakage current for the series-connected transistor chain. As such, the library optimization system adjusts gate lengths of transistors that are not part of the transistor series chains having a relatively large amount of same type transistors.

Gate length upsizing for low leakage standard cells

Multi-bit data flip-flops are disclosed that provide bit initialization through propagation of scan bits. Input multiplexers are configured to select between input data bits and input scan bits based upon mode select signals. Master latches receive and latch outputs from the input multiplexers. Slave latches receive and latch outputs from the master latches and also provide propagated input scan bits to the input multiplexers. A first state for the mode select signals selects the input data bits for a data mode of operation, and a second state for the mode select signals selects the input scan bits for a scan mode of operation. Further, the input multiplexers, master latches, and slave latches are configured to operate in an initialization mode to pass a fixed input scan bit through the multi-bit data flip-flop based upon initialization signals (e.g., set and/or reset signals).

Multi-bit data flip-flop with scan initialization

A multi-bit flip-flop includes at least two storage stages. Each of the storage stages includes redundant latches to suppress state corruptions resulting from soft error upset at the storage stage. In addition, the multi-bit flip-flop includes a split clock path that routes different shared clock signals that control the timing of the latches. The shared split clock path reduces or eliminates the impact of soft errors on the clock signals, thereby further limiting the impact of such errors on data stored at the flip-flop. In particular, the split clock path can be distributed over disparate cells in a layout of multi-bit flip-flop, thereby reducing the likelihood that a transient charge will cause a soft error in all paths of the split clock path.

Multi-bit flip-flop with soft error suppression

A CMOS device comprises a substrate with a plurality of regions, the regions including an N-type region and a P-type region which meet each other in a PN-boundary, two or more P-type active regions embedded in the N-type region, and two or more N-type active regions embedded in the P-type region. The PN-boundary or a section of the PN-boundary is a chain of line segments. Any two adjoining line segments of the chain are angled relative to each other at their connecting point. The CMOS device can be designed using abutting standard cells. For each of two or more operating points, rise delays and fall delays associated with one or more clock cells are estimated. If the estimated rise delays and fall delays satisfy a given set of constraints, the layout of the CMOS device is accepted. Otherwise the layout is updated and a new analysis round is performed.

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Moscow, Russia

Mikhail Yurievich Semenov