Ati Technologies Ulc

Advanced Micro Devices Corporation

Ati Technologies Inc.

Mikhail Rodionov

Stephen Victor Kosonocky

Joyce Cheuk Wai Wong

Ljubisa Bajic

Steven Kommrusch

Ramesh Senthinathan

Kaushik Mazumdar

Dragoljub Ignjatovic

Oleg Drapkin

Grigori Temkine

Ashish Jain

Richard W Fung

Miguel Rodriguez

Nancy Chan

Michael Foxcroft

Paul Edelshteyn

Dirk J Robinson

Thomas Y Wong

Ronny Chan

Joyce C Wong

Karen Wan

Shirley Lam

The disclosed device includes a reference delay circuit for outputting a reference delay circuit output signal from a voltage regulated supply and a noisy delay circuit for outputting a noisy delay circuit output signal from a noisy or droopy supply. The device also includes a phase comparator circuit that is connected to the reference delay circuit and the noisy delay circuit. The phase comparator circuit outputs a phase difference between the reference delay circuit output signal and the noisy delay circuit output signal. Various other methods, systems, and computer-readable media are also disclosed.

Time domain-based power supply droop detector

An integrated circuit includes a power supply monitor, a clock generator, and a divider. The power supply monitor is operable to provide a trigger signal in response to a power supply voltage dropping below a threshold voltage. The clock generator is operable to provide a first clock signal having a frequency dependent on a value of a frequency control word, and to change the frequency of the first clock signal over time using a native slope in response to a change in the frequency control word. The divider is responsive to an assertion of the trigger signal to divide a frequency of the first clock signal by a divide value to provide a second clock signal.

Droop detection and control of digital frequency-locked loop

A power supply monitor includes a droop detection circuit which receives a digital signal and converts the digital signal to an analog signal, compares the analog signal to a monitored supply voltage, and responsive to detecting a droop below a designated value relative to the analog signal, produces a droop detection signal. The droop detection circuit includes a first comparator circuit with a series of inverters including at least a first complimentary-metal-oxide-semiconductor (CMOS) inverter with an input for receiving the analog signal and a second CMOS inverter, which are both supplied with a monitored supply voltage. The inverters operate in a crowbar mode when the monitored voltage supply is near a designated level, and each include four pull-up transistors connected in two parallel legs of two transistors, and four pull-down transistors connected in two parallel legs of two transistors.

Fast droop detection circuit

An oscillator circuit is provided that adapts to voltage supply variations. The circuit first and second delays lines connected inputs of an edge detector, one delay line supplied by a reference voltage and the other with a drooping supply voltage. The edge detector generates an output clock based on a relationship between the inputs. The output clock applied to the signal inputs of the first and second delay lines. The output clock has a voltage dependent frequency performance curve with a slope dependent at least on the second delay line delay and a delay of the edge detector. At least one of the first delay line, the second delay line, and the edge detector delay are adjusted to change the slope of the performance curve.

Adaptive DCO VF curve slope control

An output clock frequency of an adaptive oscillator circuit changes in response to noise on an integrated circuit power supply line. The circuit features two identical delay lines which are separately connected to a regulated supply and a droopy supply. In response to noise on the droopy supply, the delay lines cause a change in the output clock frequency. The adaptive oscillator circuit slows down the output clock frequency when the droopy supply droops or falls below the regulated supply. The adaptive oscillator circuit clamps the output clock frequency at a level determined by the regulated supply when the droopy supply overshoots or swings above the regulated supply.

Adaptive oscillator for clock generation

A C-element circuit for use in an oscillator or the like includes a first input terminal for receiving a first input signal, a second input terminal for receiving a second input signal, and an output latch for providing an output signal based on a relationship between the two input signals. A stack of input transistors is included with an outer pair of input transistors with gates connected to the first input terminal and an inner pair of input transistors with gates connected to a second input terminal. A balancing circuit operates to equalize a first delay of a change in the first input signal affecting the output signal with a second delay of a change in the second input signal affecting the output signal. Bypass control techniques are provided for using the C-element circuit with a single input.

Symmetrical balanced c-element

A master/slave configuration of a frequency locked Loop (FLL) decouples the process, target voltage, temperature (PVT) tracking goals of locking the loop from adapting the clock frequency in response to voltage droops in the supply. A master oscillator circuit receives a regulated supply voltage and supplies a master oscillator signal. A control circuit supplies a master frequency control signal to control a frequency of the master oscillator signal to a target frequency. A slave oscillator circuit is coupled to a regulated supply voltage and a droopy supply voltage and supplies a slave oscillator signal having a frequency responsive to a slave frequency control signal that is based on the master frequency control signal. The frequency of the second oscillator signal is further responsive to a voltage change of the droopy supply voltage.

Master/slave frequency locked loop

In a method and apparatus for using a clock generating circuit to minimize settling time after dynamic power supply voltage ramping, a clock signal may be generated using a clock generating circuit having, among other things, open feedback loop switch logic and a dynamic fast lock control signal generator. Whereupon, when in operation, the open feedback loop switch logic is responsive to a controlled change in power supply voltage condition such that a feedback loop of the clock generating circuit is opened during power supply voltage ramping (e.g., during transitions to or from battery conservation modes). In response to opening the feedback loop, the dynamic fast lock control signal generator selectively applies a stabilizing control signal to a variable clock signal generator (e.g., a voltage controlled oscillator) such that the generated clock signal can quickly lock onto the proper target frequency.

Method and apparatus for fast locking of a clock generating circuit

A circuit includes a phase lock loop circuit and a continuous phase lock loop calibration circuit. The continuous phase lock loop calibration circuit is operatively coupled to the PLL circuit and produces a continuous calibration signal based on a reference voltage from a reference voltage circuit to calibrate the PLL circuit on a continuous basis.

Phase lock loop with continuous calibration and method therefor

In an embodiment, a bias generator circuit comprises a first circuit and a second circuit. The first circuit includes a first input coupled to a voltage source and a first output that provides a first output current having a substantially non-zero temperature coefficient. The first circuit comprises a first transistor and a second transistor. The second circuit includes a second input that receives the first output current from the first circuit and a second output that provides a second output current. The second circuit comprises a third transistor and a fourth transistor. The second output current has a substantially zero temperature coefficient dependent on (i) a difference between an effective channel size of the first transistor and an effective channel size of the second transistor, and (ii) a difference between an effective channel size of the third transistor and an effective channel size of the fourth transistor.

Substantially zero temperature coefficient bias generator

A multiphase clock generating circuit includes a multiphase clock generator that produces a plurality of multiphase output signals at a first frequency and a multiphase divider with delayed reset control. The multiphase divider with delayed reset control is operatively coupled to receive the plurality of multiphase output signals at the first frequency and further operative to produce a plurality of multiphase output signals at a second frequency based on reset control information. As a result, an interface can be supplied with and switch between multiphase clock at different frequencies within a short amount of time with reduced power consumption and circuit area.

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Richmond Hill, Canada

Mikhail Rodionov