Intel Corporation

Mikhail Plotnikov

Andrey Naraikin

Christopher J Hughes

Robert Valentine

Elmoustapha Ould-Ahmed-Vall

Igor Ermolaev

Jesus Corbal

Bret L Toll

Hideki Ido

William M Brown

Milind Baburao Girkar

Xinmin Tian

Sergey Preis

Ilya Burylov

Mikhail Shiryaev

Maxim Shutov

Andrey Naraikan

Ruslan Arutyunyan

Sergey Shalnov

Andrey Naralkin

Technologies for managing data wait barrier operations include starting a receive operation associated with a receive buffer of a compute node that includes a plurality of chunks of data received from a sender compute node. Each of the plurality of chunks of data may be received in an out-of-order sequence relative to an order in which they were transmitted from the sender compute node. The compute node may determine whether a chunk of data in the receive buffer satisfies a condition to be met prior to performing one or more data wait barrier operations to be performed by the compute node to process the chunk of data and, if so, perform a partial computation over the chunk of data.

Technologies for managing data wait barrier operations

Disclosed embodiments relate to a new instruction for performing data-ready memory access operations. In one example, a system includes circuits to fetch, decode, and execute an instruction that includes an opcode, at least one memory location identifier identifying at least one data element, a register identifier, a data readiness indicator identifying at least one data access condition, and a data readiness mask, wherein the execution circuit is to, for each data element of the at least one data element, determine whether a memory request for the data element satisfies the at least one data access condition identified by the data readiness indicator, and in response to determining that the memory request for the data element does not satisfy the at least one data access condition: generate a prefetch request for the data element, and set a value in a corresponding data element position of the data readiness mask to indicate that the memory request for the data element does not satisfy the at least one data access condition.

Method and apparatus for data-ready memory operations

Systems, apparatuses and methods may provide for technology that identifies that an iterative loop includes a first code portion that executes in response to a condition being satisfied, generates a first vector mask that is to represent one or more instances of the condition being satisfied for one or more values of a first vector of values, and one or more instances of the condition being unsatisfied for the first vector of values, where the first vector of values is to correspond to one or more first iterations of the iterative loop, and conducts a vectorization process of the iterative loop based on the first vector mask.

Vectorization of loops based on vector masks and vector count distances

In an embodiment, the present invention is directed to a processor including a decode logic to receive a multi-dimensional loop counter update instruction and to decode the multi-dimensional loop counter update instruction into at least one decoded instruction, and an execution logic to execute the at least one decoded instruction to update at least one loop counter value of a first operand associated with the multi-dimensional loop counter update instruction by a first amount. Methods to collapse loops using such instructions are also disclosed. Other embodiments are described and claimed.

Collapsing of multiple nested loops, methods, and instructions

Disclosed embodiments relate to a new instruction for detecting conflicts in a set of vector elements. In one example, a system includes circuits to fetch, decode, and execute an instruction that includes an opcode, a destination vector identifier, and a source vector identifier, wherein the execution circuit is to, for each data element position of a source vector identified by the source vector identifier, determine a nearest matching data element position in the source vector storing a same data value as stored at the data element position, the nearest matching data element position located between the data element position and a least significant data element position of the source vector, and store, in a corresponding data element position of a destination vector identified by the destination vector identifier, a value identifying the determined nearest data element position.

Method and apparatus for vectorizing indirect update loops

Disclosed embodiments relate to a new instruction for performing data-ready memory access operations. In one example, a system includes circuits to fetch, decode, and execute an instruction that includes an opcode, at least one memory location identifier identifying at least one data element, a register identifier, a data readiness indicator identifying at least one data access condition, and a data readiness mask, wherein the execution circuit is to, for each data element of the at least one data element, determine whether a memory request for the data element satisfies the at least one data access condition identified by the data readiness indicator, and in response to determining that the data access condition: generate a prefetch request for the data element, and set a value in a corresponding data element position of the data readiness mask to indicate that the memory request for the data element does not satisfy the at least one data access condition.

Method and apparatus for converting scatter control elements to gather control elements used to permute vector data elements is described herein. One embodiment of a method includes decoding an instruction having a field for a source vector operand storing a plurality of data elements, wherein each of the data element includes a set bit and a plurality of unset bits. Each of the set bits is set at a unique bit offset within the respective data element. The method further includes executing the decoded instruction by generating, for each bit offset across the plurality of data elements in the source vector operand, a count of unset bits between a first data element having a bit set at a current bit offset and a second data element comprising a least significant bit (LSB). A set of control elements is generated based on the count of unset bits generated for each bit offset.

Method and apparatus for converting scatter control elements to gather control elements used to sort vector data elements

Systems, methods, and apparatuses relating to element sorting of vectors are described. In one embodiment, a processor includes a decoder to decode an instruction into a decoded instruction; and an execution unit to execute the decoded instruction to: provide storage for a comparison matrix to store a comparison value for each element of an input vector compared against the other elements of the input vector, perform a comparison operation on elements of the input vector corresponding to storage of comparison values above a main diagonal of the comparison matrix, perform a different operation on elements of the input vector corresponding to storage of comparison values below the main diagonal of the comparison matrix, and store results of the comparison operation and the different operation in the comparison matrix.

Apparatuses, methods, and systems for element sorting of vectors

A processor includes a decode circuit to decode an instruction into a decoded instruction and an execution circuit to execute the decoded instruction to sum one or more values of one or more contiguous elements of an input vector that form a block to produce an accumulated value for the block and store the accumulated value for the block in a destination vector, where an input mask dictates the one or more contiguous elements of the input vector that form the block.

Vector instruction for accumulating and compressing values based on input mask

A processor includes a decode circuit to decode an instruction into a decoded instruction and an execution circuit to execute the decoded instruction to access a first bit of a first input vector located at a bit position indicated by an element of a second input vector, stride over bits of the first input vector using a stride to access bits of the first input vector that are located at a strided bit position with respect to the first bit of the first input vector, and store the first bit of the first input vector and the bits of the first input vector that are located at a strided bit position with respect to the first bit of the first input vector as consecutive bits in a destination vector.

Strideshift instruction for transposing bits inside vector register

Loop vectorization methods and apparatus are disclosed. An example method includes generating a first control mask for a set of iterations of a loop by evaluating a condition of the loop, wherein generating the first control mask includes setting a bit of the control mask to a first value when the condition indicates that an operation of the loop is to be executed, and setting the bit of the first control mask to a second value when the condition indicates that the operation of the loop is to be bypassed. The example method also includes compressing indexes corresponding to the first set of iterations of the loop according to the first control mask.

System and method of loop vectorization by compressing indices and data elements from iterations based on a control mask

Embodiments of systems, apparatuses, and methods for instruction execution. In some embodiments, an instruction has fields for a first and a second source operand, and a destination operand. When executed, the instruction causes an arithmetic operation on broadcasted packed data elements of the first source operand and storage of results of each arithmetic operation in the destination operand, wherein the packed data elements of the first source operand to be broadcast are dictated by values of packed data elements stored in a second source operand, wherein the arithmetic operation is defined by the instruction.

Systems, apparatuses, and methods for broadcast arithmetic operations

Systems, methods, and apparatuses relating to multiple source blend operations are described. In one embodiment, a processor is to execute an instruction to: receive a first input operand of a first input vector, a second input operand of a second input vector, and a third input operand of a third input vector, compare each element from the first input vector to each corresponding element of the second input vector to produce a first comparison vector, compare each element from the first input vector to each corresponding element of the third input vector to produce a second comparison vector, compare each element from the second input vector to each corresponding element of the third input vector to produce a third comparison vector, determine a middle value for each element position of the input vectors from the comparison vectors, and output the middle values into same element positions in an output vector.

Growing community of inventors

Nizhny Novgorod, Russia

Mikhail Plotnikov