Elbrus International Limited

Mikhail L Chudakov

Boris A Babaian

Yuli Kh Sakhin

Feodor A Gruzdov

Leonid N Nazarov

Sergey A Rozhkov

Vladimir Yu Volkonskiy

Vladimir V Tikhorsky

Oleg Alexandrovich Konopleff

Andrey Alexe'evich Vechtomov

A single-chip multiprocessor system and operation method of this system based on a static macro-scheduling of parallel streams for multiprocessor parallel execution. The single-chip multiprocessor system has buses for direct exchange between the processor register files and access to their store addresses and data. Each explicit parallelism architecture processor of this system has an interprocessor interface providing the synchronization signals exchange, data exchange at the register file level and access to store addresses and data of other processors. The single-chip multiprocessor system uses ILP to increase the performance. Synchronization of the streams parallel execution is ensured using special operations setting a sequence of streams and stream fragments execution prescribed by the program algorithm.

Single-chip multiprocessor with clock cycle-precise program scheduling of parallel execution

Single-chip multiprocessor with cycle-precise program scheduling of parallel execution

The present invention decreases the delay associated with loading an array from memory by employing an asynchronous array preload unit. The asynchronous array preload unit provides continuous preliminary loading of data arrays located in a memory subsystem into a prefetch buffer. Array loading is performed asynchronously with respect to execution of the main program.

Method and system for asynchronous array loading

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Moscow, Russia

Mikhail L Chudakov