Freescale Semiconductor,inc.

Mikhail Bourgart

Sergey Sofer

Yoav Weizman

Roman Mostinski

Yefim-Haim Fefer

Edward Vaiberman

Yefim Fefer

Segey Sofer

A display controller for controlling data in an isochronous display where fluctuation of data feed latency occurs, the display controller including an input memory which receives pixel data and transmits the pixel data through a main route and a secondary route; wherein pixel data is transmitted through the main route and is processed for delivery to the display in a predetermined manner; characterized in that the secondary route comprises a memory for storing a two-dimensional section of the pixel data that corresponds at least in part to the pixel data being transmitted through the main route at that time; further characterized in that the display controller includes a detector for identifying a data feed latency event and in response there to switching the transmission of the pixel data to the secondary route and processing the pixel data through secondary route for delivery to the display such that when a data feed latency event occurs the stored two-dimensional section of the pixel data from the secondary route is displayed on the display.

Unified memory architecture and display controller to prevent data feed under-run

A device and a method for testing a variable digital delay line that includes multiple taps. The method includes providing, an input signal to the variable digital delay line and finding, for each tap out of a group of tested taps of the variable digital delay line, a variable delay unit configuration that provides a delay that is closest to a delay introduced by the tap; wherein the variable digital delay line and the variable delay unit belong to the same integrated circuit.

Method for testing a variable digital delay line and a device having variable digital delay line testing capabilities

A device and method for adjusting an impedance of an output driver of an integrated circuit; the method includes: (i) receiving, by the output driver, a first square wave signal that should be driven by the output driver to provide a second signal; (ii) monitoring, by a monitoring circuit included in the integrated circuit, the second signal during an output driver transient period resulting from a first square wave signal transient to provide a monitoring result; (iii) determining whether to adjust the impedance of the output driver in response to the monitoring result; and (iv) adjusting the impedance of the output driver in response to the determination.

Device and method for adjusting an impedance of an output driver of an integrated circuit

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Modiin, Israel

Mikhail Bourgart