Synopsys, Inc.

Mikhail Bershteyn

Olivier Coudert

Florent Sébastien Marc Emmanuel Claude Duru

Srivatsan Raghavan

Prashant Kumar Mishra

Kiran Lokhande

Gilles Pierre Rémond

Vinod Chandrasekaran

A system obtains deterministic results of netlist transformation in a multi-processor parallel computing system. The system receives a netlist. The system determines a set of components representing components with assigned identifiers. The system determines identifiers for remaining components. The system visits a component of the remaining components of the netlist in a topological order starting from the set of components. The system assigns a new identifier to the visited component. The new identifier is generated based on properties of the visited component and a connection of the visited component with at least one component of the set of components. Once the component is assigned an identifier, the system adds the component to the set of components. The system repeats these steps to assign an identifier to remaining components that are not included in the set.

Deterministic netlist transformations in a multi-processor parallel computing system

A method includes: loading a circuit design including a plurality of combinational elements and controlled by a user clock; detecting strongly connected components (SCCs) corresponding to the plurality of combinational elements in the circuit design; inserting a plurality of break registers into the circuit design, each break register being between two combinational elements of a corresponding SCC of the SCCs to break the corresponding SCC, the plurality of break registers being clocked by a relaxation clock; detecting, by a processor, during an emulation run of the circuit design, one or more value mismatches across an input pin and an output pin of one or more break registers of the plurality of break registers based on a relaxation cycle of the relaxation clock, the one or more break registers being associated with one or more SCCs exhibiting instability; and reporting an instability event based on the one or more value mismatches.

Detecting instability in combinational loops in electronic circuit designs

Described is a configuration to remove false paths from an emulation netlist in a chip design under test (DUT). The configuration identifies, in an original netlist, an original subgraph of original logic gates, a subset of inputs (TI), and a subset of outputs (TO). The configuration generates a replicated subgraph of the original subgraph, the replicated subgraph having replicated logic gates corresponding to the original logic gates. The configuration connects the TI with a first replicated logic gate to a constant propagation source and remaining inputs of the replicated logic gates with corresponding original logic gates in the original netlist. The configuration disconnects, in the original netlist, output loads of TO, and connects the output loads of TO with a corresponding equivalent TO in the replicated subgraph. The configuration deletes, in the original netlist, original logic gates unconnected with an output load for TO in the original netlist.

Non-functional loopback-paths removal from IO-pads using logic replication

A method for determining a sparse memory size during emulation, the method including: determining, by a profiler memory coupled to a user memory, that one or more pages of the user memory are used by a first test sequence of a testbench during the emulation; identifying, by the profiler memory, a first set of indexes of the one or more pages of the user memory used by the first test sequence; determining a number of unique pages of the user memory that are used by the first test sequence for the emulation based on the first set of indexes; determining, by a processor, the sparse memory size for the user memory based on the number of unique pages of the user memory that are used by the testbench for the emulation and a page size of the user memory.

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Mikhail Bershteyn