Quickturn Design Systems, Inc.

Mitsubishi Electric Research Laboratories, Inc.

Mitsubishi Electric Information Technology Center America, Inc.

Mikhail Bershteyn

Stephen Paul Sample

Michael R Butts

Jerry R Bauer

Chiahon Chien

Ross T Casley

Abhijit Ghosh

Donald Tarrodaychik

Michael Leigh Lipsie

Anurag Jain

Osamu Yamamoto

A hardware emulation system is disclosed which reduces hardware cost by time multiplexing multiple design signals onto physical logic chip pins and printed circuit board. The hardware emulation system comprises a plurality of reprogrammable logic devices, and a plurality of reprogrammable interconnect devices. The logic devices and interconnect devices are interconnected together such that multiple design signals share common I/O pins and circuit board traces through the use of multiplexing.

Emulation system with time-multiplexed interconnect

A hardware emulation system is disclosed which reduces hardware cost by time-multiplexing multiple design signals onto physical logic chip pins and printed circuit board. The reconfigurable logic system of the present invention comprises a plurality of reprogrammable logic devices, and a plurality of reprogrammable interconnect devices. The logic devices and interconnect devices are interconnected together such that multiple design signals share common I/O pins and circuit board traces. A logic analyzer for a hardware emulation system is also disclosed. The logic circuits necessary for executing logic analyzer functions is programmed into the programmable resources in the logic chips of the emulation system.

Memory circuit for use in hardware emulation system

A hardware emulation system is disclosed which reduces hardware cost by time-multiplexing multiple design signals onto physical logic chip pins and printed circuit board. The reconfigurable logic system of the present invention comprises a plurality of reprogrammable logic devices, and a plurality of reprogrammable interconnect devices. The logic devices and interconnect devices are interconnected together such that multiple design signals share common pins and circuit board traces. A logic analyzer for a hardware emulation system is also disclosed. The logic circuits necessary for executing logic analyzer functions is programmed into the programmable resources in the logic chips of the emulation system.

A method and apparatus for combining emulation and simulation of a logic design. The method and apparatus can be used with a logic design that includes gate-level descriptions, behavioral representations, structural representations, or a combination thereof. The emulation and simulation portions are combined in a manner that minimizes the time for transferring data between the two portions. Simulation is performed by one or more microprocessors while emulation is performed in reconfigurable hardware such as field programmable gate arrays. When multiple microprocessors are employed, independent portions of the logic design are selected to be executed on the multiple synchronized microprocessors. Reconfigurable hardware also performs event detecting and scheduling operations to aid the simulation, and to reduce processing time.

Method and apparatus for design verification using emulation and

The speed of a hardware-software debugger is markedly increased through the use of high speed simulators which ignore all systems operations except those where design errors are expected to manifest themselves, by skipping CPU bus cycles of no interest for the simulation, by not explicitly simulating periodic clock signals and generating only schedules of clock signals, and by caching instructions when alien computers are used in the simulation process to eliminate decoding of the instructions of the target computer.

Hardware-software debugger using simulation speed enhancing techniques

In integrated circuit testing which involves partitioning of tailored test vectors into subsets and filling of the subsets with similar vectors starting with vectors close to the initially selected vector and continuing to add vectors farther away until an optimal number of vectors are in the subset, a system is provided for selecting a number of test vectors to go into a subset by using a unique 'distance' measure to measure how far away the candidate vector is from what is already in the subset. Distance determination involves comparing the candidate vector with the weights generated from randomization of the previous vectors in the subset. Having provided a unique distance or 'closeness' measure for each candidate vector, the distance of a number of candidate vectors is ascertained. The one with the smallest distance from those vectors already in the subset is selected for determination as to whether its inclusion in the subset results in more rapid and accurate fault detection. This determination is made based on a prediction algorithm which includes calculation of the mathematical expectation of the number of tailored vectors not appearing in a weighted random sequence.

System for testing of digital integrated circuits

In integrated circuit testing, a system is provided for reducing testing time by decreasing the number of test vectors or patterns while maintaining high fault coverage through utilizing lists of undetected faults in an integrated circuit to determine the optimal weighting for a weighted random pattern generator that is used for testing the integrated circuit. Undetected faults are derived from testing a model of the circuit under test with a uniform weight pattern, with the circuit modified with each fault from a list of anticipated faults. Undetected faults from this first pass are used to generate another set of weights which are then used to apply test signals to the circuit for generating a further but diminished list of undetected faults. This process is iterative and is continued until the number of undetected faults is either zero or some low acceptable number. The set of weights generated in this iterative process is then used in the weighted random pattern generator for applying test signals to actual circuits. As part of this process, for circuit elements requiring diametrically opposed input signals, such as AND gates and OR gates where a single set of input signals is inappropriate, this conflict is resolved through detecting the fact that for one part, all faults are detected, and then generating test vectors suitable for the opposite circuit. This allows the testing of circuits piece by piece.

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Campbell, CA, United States of America

Mikhail Bershteyn