Lsi Logic Corporation

Mike T Liang

Virinder Singh

Ramoji Karumuri Rao

Chun Chan

Mike C Loo

Kevin R LeClair

Tammy T Huang

Myron J Buer

Sudhakar Sabada

Tile-based routing between a bump pad and an input/output (I/O) device for implementation on a flip-chip integrated circuit (IC) die. A trace is routed between the bump pad and a position corresponding to a first I/O slot, the first I/O slot being at least partially occupied by the I/O device. A position is obtained for a device pad for the I/O device. The trace is then extended into an area corresponding to the position obtained for the device pad. It is a feature of this aspect of the invention that the trace extension extends the trace into a pad area for a second I/O slot, the second I/O slot being at least partially occupied by the I/O device. The invention also concerns a flip-chip integrated circuit (IC) die that includes a bump pad, an input/output (I/O) device, and a device pad electrically connected to the I/O device and disposed vertically adjacent to a portion of the I/O device. Also provided is an electrically conductive trace, including a first portion between the bump pad and a first position, the first position corresponding to a portion of the I/O device and being horizontally offset from the device pad, and also including a second portion between the first position and a second position corresponding to the device pad.

Flip-chip integrated circuit routing to I/O devices

Provided is a technique for designing an integrated circuit die which includes a semiconductor layer, a primary metal layer, a horizontal metal layer and a vertical metal layer. Electronic components are laid out on the semiconductor layer, and a primary power distribution network for distributing power to the electronic components is laid out on the primary metal layer. Then, a uniform trunk width is calculated for all trunks in a power mesh based on a desired maximum voltage drop for the generated electronic component layout. Finally, horizontal power trunks are laid out on the horizontal metal layer and vertical power trunks are laid out on the vertical metal layer using the calculated uniform trunk width, so as to form the power mesh, and an electrical connection is specified between the power mesh and the primary power distribution network.

Integrated circuit design incorporating a power mesh

A method for laying out input/output (I/O) pairs, each including an I/O cell and a pad, on an integrated circuit die. Size information is obtained for each of a first I/O pair and a second I/O pair. A minimum pad spacing criterion is obtained which specifies a minimum distance between the pad in the first I/O pair and an element of the second I/O pair, and the first I/O pair and the second I/O pair are laid out so as to satisfy the minimum pad spacing criterion. Also provided is a method for laying out pads for input/output (I/O) cells on an integrated circuit die in which size information is obtained for each of a first I/O cell pad and a second I/O cell pad. A minimum pad spacing criterion is obtained, and the first I/O cell pad and the second I/O cell pad are laid out so as to satisfy the minimum pad spacing criterion.

I/O device layout during integrated circuit design

A flip-chip integrated circuit die includes a semiconductor substrate, electronic components implemented on the semiconductor substrate, several plural metal layers, wires routed between the electronic components on the metal layers, a top layer, and bump pads arranged in a hexagonal array on the top layer. According to another aspect, the invention is directed to flip-chip integrated circuit design, in which a circuit description is input and standardized cells which correspond to electronic components in the circuit description are obtained. The standardized cells are laid out on the surface of the die using a rectangular-based layout technique, and bump pads are laid out in a hexagonal array.

Hexagonal arrangements of bump pads in flip-chip integrated circuits

Integrated circuit chip (IC) design and fabrication is a complex process requiring many stages including elaborate cell placement processes. The present invention provides a method and apparatus to facilitate the placement of cells on the surface of an integrated circuit device. Specifically, the invention involves placement of one type of cells (such as logic cells, I/O cells or scan cells) apart from other types of cells. The present invention facilitates the placement of such cells by first parsing the netlist to remove all cells other than the specific type of cells that are to be placed.

Method and apparatus for netlist filtering and cell placement

Provided is a semiconductor flip chip die metal layout which provides a flat UBM where surface metal pads are narrower than UBMs in order to accommodate decreased die pitch. This is achieved by depositing a metal region adjacent to and closely spaced from the pad which, together with the pad, is capable of providing a substrate that will result in a substantially flat passivation layer surface on which the UBM is subsequently deposited. The adjacent closely spaced metal region may be provided by bringing metal traces closer to a reduced size surface metal pad (into the die surface area underlying the UBM), and/or by depositing dummy metal similarly near the pad. The dummy metal may also be deposited over the whole chip surface area not occupied by other electrical components.

Semiconductor die metal layout for flip chip packaging

Method for I/O device layout during integrated circuit design

An arrangement of bump pads for use on a face of a flip-chip semiconductor die. The arrangement comprises four corner regions, each corner region comprising multiple I/O bump pads and power bump pads. The corner regions are specialized bump arrangements depending upon the size of the die, signal to power ratios, and the core power requirements. The die arrangement also comprises multiple edge regions having multiple I/O bump pads and power bump pads. The edge regions are located along the edges of the die and are interleaved between the corner regions. The dimensions of the corner regions and the edge regions depend upon the power to signal ratio of the region. Also provided is a core power region having multiple power bump pads, centrally located within the edge regions and the corner groups. Core requirements mandating an odd number of rows and columns of bumps for the core require a special 'checkerboard' arrangement also provided. Connections between the bumps and the edge of the die surface are shown. According to a second embodiment, there is provided a die surface arrangement with two power bumps, one live voltage, or power, bump and one ground bump, and multiple I/O bumps, all bumps linearly aligned, with the ground and power bumps both located intermediate between the I/O bumps. The ground, power, and I/O bumps form an array, and this array is replicated linearly across the die surface forming a linear array arrangement having alternately directed redistribution traces. The die surface arrangement comprises multiple linear array arrangements interspersed with multiple linearly aligned core power bumps.

Flip chip bump distribution on die

Method for distributing connection pads on a semiconductor die

A semiconductor memory layout definition for connection to a power supply bus in an integrated circuit layout pattern. The layout definition includes an outline and a plurality of power supply conductor segments within the outline. At least one of the power supply conductor segments has a direct strap identifier which indicates a desired attachment to the power supply bus. The direct strap identifier is passed to a routing design tool which routes a direct strap conductor from the power supply bus to the power supply conductor segments having the direct strap identifier.

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Milpitas, CA, United States of America

Mike T Liang