Micron Technology Incorporated

Mike Pearson

Tim G Damon

Blane Holden

Matt Adsitt

Dan Dean

Brent Keeth

Troy A Manning

Terry R Lee

Kevin J Ryan

Chris G Martin

Thomas W Voshell

Wallace E Fister

Kim M Pierce

A system is disclosed for evaluating relevant data across independent test sequences and providing a consumable output to give a tester an accurate account of the test data. A method for reporting the results of the test processes includes several steps. First, repair, trending, characterization, timing and engineering data for two separate test sequences are read. Next, the data is compared. Also, an analytical report of the test data comparisons is assembled and output.

System for evaluating and reporting semiconductor test processes

A memory device includes an output data path that transfers data from an I/O circuit coupled to a memory array to an output tri-state buffer. A comparing circuit compares data from the I/O circuit to a desired data pattern. If the data does not match the desired pattern, the comparing circuit outputs an error signal that is input to the output buffer. When the output buffer receives the error signal, the output buffer is disabled and outputs a tri-state condition on a data bus. Since the error signal corresponds to more than one data bit, the tri-state condition of the output buffer is held for more than one tick of the data clock, rather than only a single tick. Consequently, the tri-state condition remains on the bus for sufficiently long that a test system can detect the tri-state condition even at very high clock frequencies.

Method and apparatus for memory array compressed data testing

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Boise, ID, United States of America

Mike Pearson