Intel Corporation

Lucent Technologies Inc.

Alcatel-lucent USA Inc.

Alcatel Lucent

Mike Morrison

Eric T Anderson

Philip Arnold Ferolito

Gregory S Mathews

Kushagra V Vaid

James Jiahua Yu

Fred Gruner

Gunes Aybay

Nazar A Zaidi

Ricardo Ramirez

James Bauman

Umberto Santoni

John Rigby

Michael Mroczek

Mindong Chen

A technique for classifying traffic at a network node includes programming multiple on-chip memory arrays with identical search entries, receiving multiple packets, and distributing classification searches related to the packets among the multiple on-chip memory arrays. In an embodiment, the on-chip memory arrays are content-addressable memory (CAM) arrays. In another embodiment, the distributing of classification searches related to the packets is performed in an alternating fashion with respect to a fixed order.

Classifying traffic at a network node using multiple on-chip memory arrays

A packet-based traffic switching system with error detection and correction without taking the system offline. The system tests offline paths without interfering with other online paths. Also, the system tests online paths even while no data cell traffic is sent over the paths. The system responds to the addition or removal of paths or path components without interrupting cell traffic. The system detects and selectively flushes defective paths without impacting paths that are working properly. The system initializes new switching fabrics automatically without using software to set values. Thus, the system tests online paths and corrects errors without going offline.

Testing and error recovery across multiple switching fabrics

A traffic forwarding system that uses a multicast start-of-packet (SOP) pointer to enqueue a multicast packet in packet queues. The system receives cells, assigns pointers to the cells, and stores the received cells in memory. The system assigns multicast SOP pointers to multicast SOP cells. The system reassembles cells into packets and enqueues the packets in packet queues for forwarding. A multicast packet is enqueued in a plurality of packet queues. The memory in which the multicast packet is stored is released after the multicast packet is dequeued from each of the plurality of packet queues.

Multicast packet queuing

A two stage rate shaping and scheduling system and method is implemented to control the flow of traffic to at least one output interface. The system and method involves initially queuing incoming packets into type-specific queues and applying individual rate shaping rules to each queue. A first stage arbitration is performed to determine how traffic is queued from the type-specific queues to interface-specific queues. Packets that win arbitration and pass the applied rate shaping rules are queued in interface-specific queues. Rate shaping rules are applied to the interface-specific queues. The interface-specific queues are further distinguished by priority and priority-specific and interface-specific rate shaping rules are applied to each queue. A second stage arbitration is performed to determine how different priority traffic that is targeting the same output interface is dequeued in response to interface-specific requests.

Flexible multilevel output traffic control

A system for efficiently reassembling packets from cells received on independent switching fabrics according to a serial high speed interface (HSI) protocol. The system includes redundancy in that fabrics may be removed by skipping the fabrics in striping and reassembly sequences. When fabrics are added, the fabrics are included in the striping and reassembly sequences. The system is efficient due in part to in-order transmission of cells serially across multiple fabrics. Full fabric bandwidth is thereby utilized without reordering overhead. Since packets are striped across all available fabrics, load is balanced across the fabrics.

Using reassembly queue sets for packet reassembly

A technique for classifying traffic at a network node involves programming a content addressable memory (CAM) array with multiple class-specific entries, where each of the class-specific entries has an associated traffic class, obtaining a protocol-independent key field from an incoming packet, and searching the programmed CAM array with the protocol-independent key field to identify an associated traffic class of the incoming packet. In another embodiment, each of the class-specific entries has an associated traffic distribution policy, which may be applied to an incoming packet.

Classifying and distributing traffic at a network node

A system for efficiently sending cells in-order to independent switching fabrics according to a serial high speed interface (HSI) protocol. The system includes redundancy in that fabrics may be removed by deleting the fabrics from striping and reassembly sequences. When fabrics are added, the fabrics are added to the striping and reassembly sequences. The system is efficient due in part to in-order transmission of cells serially across multiple fabrics. Full fabric bandwidth is thereby utilized without reordering overhead. Since packets are striped across all available fabrics, load is balanced across the fabrics.

Optimal load balancing across multiple switching fabrics

A system and method for aligning an instruction stream is described. The system comprises a rotator logic unit for rotating data bytes of the instruction stream. A shifter logic unit is used for shifting the data bytes to the start of a instruction based upon a length of an immediately prior instruction.

Method and system for a two stage pipelined instruction decode and alignment using previous instruction length

A system and method for decoding the length of a macro instruction is described. In one embodiment, the system comprises an opcode-plus-immediate logic unit to generate a first length value, the first length value comprising a length of an opcode plus a length of intermediate data. A memory-length logic unit generates a second length value, the second length value comprising a potential length of a memory displacement, the opcode-plus-immediate logic unit and memory-length logic unit operating in parallel. In addition, the system comprises a length-summation logic unit to sum the first length value and the second length value if the second length value is present.

Method and system for instruction length decode

Only one pipe in superscalar microprocessor contains particular functional logic necessary to process a specific instruction. When the specific instruction appears in an instruction stream, the microprocessor replicates the specific instruction so that there are as many identical instructions in the stream as there are pipes. The identical instructions appear contiguously in the instruction stream. Each identical instruction is processed by a different one of the pipes. The pipe with the particular functional logic performs the necessary operations for the specific instruction while the other pipes treat the instruction as a null operation.

Method and apparatus for efficient pipelining

A microprocessor capable of delaying the deallocation of an arithmetic flags register is described. A system processes instructions of a first instruction set architecture which has an arithmetic flags register. The system also processes instructions of a second instruction set architecture which is not compatible with the first instruction set architecture. In order to process a first instruction of the first instruction set architecture that implicitly updates the arithmetic flags register, the arithmetic flags register shares a physical destination register with a general register containing a result for the first instruction. An instruction that does not update the arithmetic flags but would deallocate the register containing the arithmetic flags triggers the delayed deallocation mechanism of the present invention.

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Sunnyvale, CA, United States of America

Mike Morrison