Vivante Corporation

Verisilicon Holdings Company Ltd.

Verisilicon Microelectronics (shanghai) Co., Ltd.

Verisilicon Microelectronics (nanjing) Co., Ltd.

Mike M Cai

Lefan Zhong

Jean-Didier Allegrucci

Cheng Chi

Anthony Ya-Nai Tai

Ming Chen

J D Allegrucci

Jiangbo Li

Yi Zhang

Frido Garritsen

Huiming Zhang

Lin Tan

Keith Lee

Frido Garristen

Kui Qin

Yijun Li

Jd Allegrucci

The present disclosure provides a vector graphics data processing method, system, medium, and vector graphics processing device. The method includes the following operations: building a vector primitive path intersection data structure (PIDS) based on coordinates of path intersections (PIs); when a new PI is generated, comparing information of the new PI to information of existing PIs corresponding to an X coordinate or Y coordinate of the new PI; and storing the information of the new PI at a corresponding position in the PIDS corresponding to the X coordinate or Y coordinate of the new PI based on a result of the comparing. Only effective PI data are saved, thereby reducing memory footprint and memory bandwidth, and improving vector graphics processing performance.

Method, system, medium, and device for processing vector graphics primitives to determine path edge order for path filling

The present disclosure provides a tessellation data processing method, system, medium and vector graphics processing device. The method includes: constructing a data structure including a content table and information tables in memory; when a vector line generated by tessellation intersects an horizontal/vertical line to obtain a new intersection, reading an address and number of Xnodes or Ynodes of an information table in the content table corresponding to a row/column corresponding to the Y/X coordinate of the intersection; according to the address of the information table and the number of X/Ynodes of the information table, reading corresponding X/Ynodes from the memory; comparing information of the intersection with the X/Ynodes, and updating the X/Ynodes in the information table, or adding an X/Ynode to the information table at a position corresponding to the Y/X coordinates. The tessellation data processing method, system, medium and vector graphics processing device of the present disclosure only require recording fill information of effective intersections generated by tessellation, and do not require recording fill information of all pixels, thereby reducing memory footprint and increasing vector graphic rendering performance.

Tessellation data processing method, system, medium and vector graphics processing device

The present disclosure provides a tessellation data processing method, system, media, and vector graphics processing device. The method includes: according to specified coordinates of intersections, creating different levels of cache tables, wherein the intersections result from vector lines generated by tessellation intersecting lines parallel to an x-axis or y-axis; storing in a content table addresses of information tables in memory, storing in a lowest level cache table an address of the content table in the memory, and storing an address of the lowest level cache table in the memory in a cache table one level higher than the lowest level cache table. The tessellation data processing method, system, media, and vector graphics processing device of the present disclosure store effective data in multi-level lookup tables based on coordinates of intersections, effectively reduce memory footprint, support multi-channel tessellation processing, and enhance the performance of vector graphics rendering.

Mathematical functions are computed in a single pipeline performing a polynomial approximation (e.g. a quadratic approximation, or the like); and one or more data tables corresponding to at least one of the RCP, SQRT, EXP or LOG functions operable to be coupled to the single pipeline according to one or more opcodes; wherein the single pipeline is operable for computing at least one of RCP, SQRT, EXP or LOG functions according to the one or more opcodes. SIN and COS are also computed using the pipeline according to the approximation ((&#x2212;1)^IntX)*Sin(&#x3c0;*Min(FracX, 1.0&#x2212;FracX)/Min(FracX, 1.0&#x2212;FracX). A pipeline portion approximates Sin(&#x3c0;*FracX) using tables and interpolation and a subsequent stage multiplies this approximation by FracX. For input arguments of x close 1.0. LOG 2(x&#x2212;1)/(x&#x2212;1) is computed using a first pipeline portion using tables and interpolation and subsequently multiplied by (x&#x2212;1). A DIV operation may also be performed with input arguments scaled up to avoid underflow as needed.

Systems and methods for computing mathematical functions

Disclosed are new approaches to Multi-dimensional filtering with a reduced number of memory reads and writes. In one embodiment, a filter includes first and second coefficients. A block of a data having width and height each equal to the number of one of the first or second coefficients is read from a memory device. Arrays of values from the block are filtering using the first filter coefficients and the results filtered using the second coefficients. The final result may be optionally blended with another data value and written to a memory device. Registers store results of filtering with the first coefficients. The block of data may be read from a location including a source coordinate. The final result of filtering may be written to a destination coordinate obtained by rotating and/or mirroring the source coordinate. The orientation of arrays filtered using the first coefficients varies according to a rotation mode.

Low power and low memory single-pass multi-dimensional digital filtering

A system to process a plurality of vertices to model an object. An embodiment of the system includes a processor, a front end unit coupled to the processor, and cache configuration logic coupled to the front end unit and the processor. The processor is configured to process the plurality of vertices. The front end unit is configured to communicate vertex data to the processor. The cache configuration logic is configured to establish a cache line size of a vertex cache based on a vertex size of a drawing command.

System and method for dynamically reconfiguring a vertex cache

A system to reduce aliasing in a graphical image includes an edge detector configured to read image depth information from a depth buffer. The edge detector also applies edge detection procedures to detect an object edge within the image. An edge style detector is configured to identify a first edge end and a second edge end. The edge style detector also identifies an edge style associated with the detected edge based on the first edge end and the second edge end. The system also includes a restoration module configured to identify pixel data associated with the detected edge and a blending module configured to blend the pixel data associated with the detected edge.

Anti-aliasing system and method

Mathematical functions are computed using a single hardware pipeline that performs polynomial approximation of second degree or higher. The single hardware pipeline includes multiple stages. Several data tables are used on the computations. The data tables are associated with a reciprocal, square root, exponential, or logarithm function. The data tables include data associated with implementing the associated function. The single hardware pipeline computes at least one of the functions associated with the data tables.

A graphic processing system to compute a texture coordinate. An embodiment of the graphic processing system includes a memory device, a texture coordinate generator, and a display device. The memory device is configured to store a plurality of texture maps. The texture coordinate generator is coupled to the memory device. The texture coordinate generator is configured to compute a final texture coordinate using an arithmetic operation exclusive of a division operation. The display device is coupled to the texture coordinate generator. The display device is configured to display a representation of one of the plurality of texture maps according to the final texture coordinate. Embodiments of the graphic processing system facilitate a simple hardware implementation using operations other than division.

Coordinate computations for non-power of 2 texture maps

An apparatus and method is provided for data processing where power is automatically controlled with a feed back loop with the host processor based on the internal work load characterized by performance counters. The host automatically adjusts internal frequencies or voltage level to match the work load. The feedback loop allows tuning of frequency or voltage controlling power dissipation.

Processing data using multiple levels of power control

A hierarchical tile-based rasterization method is disclosed. The inventive rasterization algorithm rasterizes pixels in hierarchical rectangles or blocks. The method includes: walking a plurality of tiles of pixels and determining if each tile is valid; breaking each valid tile into a plurality of subtiles and determining if each subtile is valid; breaking each valid subtile into a plurality of quads and determining if each quad is valid; and rendering pixels for each valid quad. These hierarchical levels of block validations are performed in parallel. The inventive rasterization algorithm is further implemented in hardware for better performance.

Hierarchical tile-based rasterization algorithm

A graphic processing system to compute a texture level of detail. An embodiment of the graphic processing system includes a memory device, a driver, and level of detail computation logic. The memory device is configured to implement a first lookup table. The first lookup table is configured to provide a first level of detail component. The driver is configured to calculate a log value of a second level of detail component. The level of detail computation logic is coupled to the memory device and the driver. The level of detail computation logic is configured to compute a level of detail for a texture mapping operation based on the first level of detail component from the lookup table and the second level of detail component from the driver. Embodiments of the graphic processing system facilitate a simple hardware implementation using operations other than multiplication, square, and square root operations.

Apparatus and method for texture level of detail computation

A distributed clipping scheme is provided, view frustum culling is distributed in several places in a graphics processing pipeline to simplify hardware implementation and improve performance. In general, many 3D objects are outside viewing frustum. In one embodiment, clipping is performed on these objects with a simple algorithm in the PA module, such as near Z clipping, trivial rejection and trivial acceptance. In one embodiment, the SE and RA modules perform the rest of clipping, such as X, Y and far Z clipping. In one embodiment, the SE module performs clipping by way of computing a initial point of rasterization. In one embodiment, the RA module performs clipping by way of conducting the rendering step of the rasterization process. This approach distributes the complexity in the graphics processing pipeline and makes the design simpler and faster, therefore design complexity, cost and performance may all be improved in hardware implementation.

Growing community of inventors

Newark, CA, United States of America

Mike M Cai