Intel Corporation

Mike J Tripp

R Tim Frodsham

Nasser A Kurd

Alper Ilkbahar

Donald B Alpert

David J O'Brien

Bruce Querbach

Tak Ming Mak

Robert S Dreyer

Ali Muhtaroglu

Nimish H Modi

Amjad M Khan

Anne Meixner

Sarah E Bates

Jeff Wight

Marco A Vindas Vargas

Rajay R Pai

Luis Briceno Guerrero

Embodiments of the invention provide a logic simulation having a controllable delay model implemented therein that may be used to validate AC I/O loopback design in a pre-silicon environment by introducing delay models that allow the logic simulators to simulate analog behavior. For one embodiment of the invention, a fixed processor ratio is selected and delay statements of the hardware description language correspond to a specific time delay. These fixed values provide the ability to accurately determine and adjust delay in an analog simulation.

Methods and apparatuses for validating AC I/O loopback tests using delay modeling in RTL simulation

According to one embodiment, a method of conducting a switching state (AC) loop back test at a buffer circuit comprises varying the relationship between the generation of strobe signals at a strobe input/output (I/O) circuit of a first group of I/O circuits and the reception of data at the first group of I/O circuits receiving the strobe signals fails, and comparing the time at which the first I/O circuit fails with a predetermined timing performance for the first group of I/O circuits. Subsequently, it is determined whether the first group of I/O circuits satisfies the predetermined timing performance.

Method and apparatus to structurally detect random defects that impact AC I/O timings in an input/output buffer

In one embodiment, an integrated circuit including a plurality of input/output (I/O) buffers is disclosed. The integrated circuit contains a plurality of I/O buffers. Each of the I/O buffers include an I/O test circuit that generates test pattern signals whenever the integrated circuit is operating in a loopback test mode. According to a further embodiment, the integrated circuit includes one or more programmable delay circuits coupled to the I/O buffers that permit switching state (AC) loopback timing tests to be conducted.

Method and apparatus for conducting input/output loop back tests using a local pattern generator and delay elements

A microprocessor is disclosed herein having an external command mode for directly accessing the execution unit, responsive to externally generated commands and instructions. An external instruction path is provided, as well as a conventional processor-driven instruction path. A multiplexer is provided that selects which of the instruction paths is actually supplied to the execution unit. Using the external command mode, the user can examine and modify registers, memory, and I/O space without otherwise affecting their contents. Any instruction executable by the execution unit is executable in the external command mode. Because direct access is provided into the execution unit, there is no implicit updating that would otherwise affect the state of the processor and require saving to an alternate memory. The present invention is implemented with a conventional test access port designed in accordance with the IEEE 1149.1 boundary scan standard, with modification to include an instruction register, a data register, and control logic. The external command mode is applicable to single and multiple pipeline processors. The circuit described herein includes several selectors for selecting between the probe mode and the processor-driven mode of operation, including an external pin, an external command, and a debug exception. For ascertaining if the circuit is in the external command mode, an acknowledge pin is provided to indicate when the execution unit is ready to accept an instruction in the probe model.

Microprocessor with an external command mode for diagnosis and debugging

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Forest Grove, OR, United States of America

Mike J Tripp