Xitore, Inc.

Smart Modular Technologies, Inc.

Intelligent Memory Limited

Netlist, Inc.

Executive Advisory Firm LLC

Mike Hossein Amidi

Satyadev Kolli

Fariborz F Roohparvar

Kelvin Alberto Marino

Michael Rubino

Hossein Hashemi

Jayesh R Bhakta

Jeffrey C Solomon

Scott H Milton

Chi-She Chen

Vahab Alemzadeh

Ali Ghiasi

Robert S Pauley, Jr

Douglas Lane Finke

Satyanarayan Shivkumar Iyer

Alessandro Fin

Larry C Alchesky

A memory testing device uses a master control unit to concurrently operate multiple, intelligent, slave control units (SCUs). SCUs can have one or more processing unit(s) (i.e. Finite State Machines, micro controllers, processors) capable of testing volatile and/or non-volatile memory devices connected into one or more DUT devices. Additionally, SCUs can have an operating system that can install and run host applications locally within each SCU unit to mimic host applications environments, along with performing regular memory testing. SCUs can operate using software and/or firmware, or hardware without reliance on firmware or software.

Apparatus, systems, and methods for dynamically reconfigured semiconductor tester for volatile and non-volatile memories

A memory testing device uses a master control unit (MCU) to concurrently operate multiple, intelligent, slave control units (SCUs). The MCU or an SCU translates memory addresses of a device under test (DUT) into a matrix. The SCU accumulates error data by testing a test bit of the memory across multiple cells of the matrix, the accumulated error data is post-processed to determine if the test bit is faulty, and the process is repeated for additional test bits. The post-processed data is analyzed to identify one or more of the test bits as faulty, and then include in a test log preferably only a single instance of a memory address that corresponds to each of the one or more faulty test bits.

Systems and methods for reducing error log required space in semiconductor testing

A memory testing device uses a master control unit to concurrently operate multiple, intelligent, slave control units (SCUs). SCUs have one or more processing unit(s) (i.e. Finite State Machines, micro controllers, processors) capable of processing one or more firmware with or without operating system (i.e. bare-metal, embedded OS, RTOS (real time operating system)) to perform a series of task defined by firmware(s) for testing volatile and/or non-volatile memory devices connected into one or more DUT devices plus SCU has capability of having operating system and install and run host applications locally within each SCU units to mimic host applications environments along with performing regular memory testing.

Apparatus, systems, and methods for reducing memory product testing failures, including a memory tester that keeps track of how often a memory product is inserted into a memory product receiving component of the memory tester, and uses that information to trigger replacing the memory product receiving component when the count reaches or exceeds a threshold. The electronics can be arranged to increase the count even if a memory product is inserted into the memory product receiving component while the memory tester is powered off.

Autonomous detection of memory insertion into test equipment without requiring power to the tester unit

A hybrid memory system provides rapid, persistent byte-addressable and block-addressable memory access to a host computer system by providing direct access to a both a volatile byte-addressable memory and a volatile block-addressable memory via the same parallel memory interface. The hybrid memory system also has at least a non-volatile block-addressable memory that allows the system to persist data even through a power-loss state. The hybrid memory system can copy and move data between any of the memories using local memory controllers to free up host system resources for other tasks.

Apparatus, system, and method of byte addressable and block addressable storage and retrieval of data to and from non-volatile storage memory

A secure memory that couples to a host memory controller via a host memory interface remains secure by permanently altering a security key when a hardware interrupt detector detects that a signal between the host memory interface hardware and the host memory controller hardware is interrupted. Such an interruption could be, for example, a blackout, a brownout, or a person decoupling any portion of the host memory interface, even pins that are normally unused by a standard memory module, such as a DRAM, MRAM, or SSD module.

Apparatus, system, and method of securitization of memory modules against malicious acts

Apparatus, system, and method of byte addressable and block addressable storage and retrival of data to and from non-volatile storage memory

A system, method and apparatus to provide searching capabilities of a given queue to all of requested search patterns in a non-volatile storage unit with compressed data without decompression thereof. In one embodiment the invention provides system, method and apparatus to execute one or more queued search request of one or more search pattern for one or more non-volatile storage units without decompression of non-volatile storage units compressed data in sequence or in parallel, in order or out of order from the queue. In another embodiment the system, method, and apparatus utilizes a software storage device driver scheduler to distribute the search queues to one or more non-volatile storage units in series or in parallel, in order or out of order, in standard or virtualized operating system capable environments.

Apparatus, system, and method for searching compressed data

A computer memory device and a method of storing data are provided. The computer memory device includes a parallel memory interface configured to be operatively coupled to a system memory controller, to receive data and commands including logical addresses from the system memory controller, and to transmit data to the system memory controller. The parallel memory interface is configured to respond to the commands from the storage device driver of a computer processing unit. The computer memory device further includes an address translation circuit configured to receive the logical addresses from the parallel memory interface and to translate the received logical addresses to corresponding physical addresses. The computer memory device further includes a non-volatile memory operatively coupled to the parallel memory interface and the address translation circuit. The non-volatile memory is configured to receive the physical addresses and the data and to store the data at memory locations of the non-volatile memory corresponding to the physical addresses.

Apparatus, system, and method for non-volatile data storage and retrieval

A non-volatile memory system performs data operations efficiently for a host system by having a multi-layered architecture. The system includes multiple local controllers that are connected to an array of non-volatile memories, a master controller connected to the multiple local controllers, and an internal processing unit that communicates with the master controller. The internal processing unit receives data operation requests from the host system and generates groups of related operations. A group of related operations include a set of common addresses and multiple commands. The internal processing unit sends a group of related operations to the master controller, which in turn broadcasts the group of related operations to the local controllers, by first broadcasting addresses to the local controllers, broadcasting a first command to the local controllers, and then broadcasts a second command to the local controllers while the local controllers are still executing the first command.

Apparatus, system, and method of look-ahead address scheduling and autonomous broadcasting operation to non-volatile storage memory

An improved way of communicating data operation commands within a non-volatile storage controller is presented. The non-volatile storage controller includes an internal processing unit that is communicatively coupled with an associated host system, a master controller, and a plurality of local controllers that are communicatively coupled with a non-volatile memory. Upon receiving a series of data operations commands from the host system, the internal processing unit is configured to apply address shadowing when communicating the series of commands to the master controller such that the internal processing unit does not need to repetitively send the same set memory addresses to the master controller when issuing the series of commands.

Apparatus, system, and method of sequencing, shadowing, and queuing operations in a non-volatile storage memory

Data stored in a volatile memory subsystem is backed up redundantly into first and second channels of a non-volatile memory subsystem. The data is retrieved from the volatile memory subsystem upon detection of a trigger condition indicative of real or imminent power loss or reduction and multiple copies are stored in dedicated non-volatile memory channels. The stored copies may be error checked and corrected, and re-written if necessary. The redundantly backed up data can be subsequently retrieved from the non-volatile memory subsystem, error-corrected, and an error-free copy communicated to the volatile memory subsystem.

Redundant backup using non-volatile memory

A fast and lean way of performing logical-to-physical address translation is presented. A logical address is divided into a most significant bits portion and a least significant bits portion. Instead of using the entire logical address to locate an entry in an address translation table, only the most significant bits portion of the logical address is used, which substantially reduces the size of the address translation table. The entry includes a most significant bits portion of a physical volatile memory address and a most significant bits portion of a physical non-volatile memory address. The actual physical volatile memory address and the actual physical non-volatile memory address can be derived by combining the most significant bits portions of the addresses stored in the address translation table entry with the least significant bits portion of the logical address.

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Lake Forest, CA, United States of America

Mike Hossein Amidi