General Electric Company

Mike F Chang

Harvey E Cline

Thomas R Anthony

Alfred Roesch

Richard W Kennedy

Hamza Yilmaz

David K Hartman

George C Pifer

Bantval J Baliga

King Owyang

Robert G Hodgins

Peter V Gray

Robert S Wrathall

Davis K Hartman

Henri B Assalit

George L Gauffreau

A self aligned method of fabricating a self aligned semiconductor device employs an initial step in which a first window having an inner perimeter and outer perimeter is opened through a first protective layer situated atop a semiconductor substrate, to divide the substrate into three separate zones. The window exposes a first surface portion of the semiconductor substrate and circumferentially defines or encompasses a second central portion of the protective layer as well as a second unexposed surface portion of the substrate. A third surface portion of the substrate lies beyond the outer perimeter of the first window. Precisely aligned substrate regions of the same or different conductivity type can be established by using differentially etchable materials to mask designated surface portions of the substrate.

Method of fabricating self aligned semiconductor devices

A semiconductor device, such as a MOSFET or IGT, with a deep base region having a high dopant concentration at least as high as 5.times.10.sup.19 atoms per cubic centimeter and a method of fabrication are disclosed. The novel method involves formation of the deep base region at a later stage in the fabrication and reduces the leaching of dopant from the deep base region, as well as achieving greater control over the dopant concentration in the deep base region. Further, the increased dopant concentration in the deep base region lowers the base shunt resistance of the device to provide improved electrical ruggedness. For IGTs, parasitic thyristor action is reduced.

Semiconductor device and method of fabrication

During fabrication of an insulated gate device, a drain-forming dopant having a relatively low diffusion coefficient is implanted along a substrate surface which overlaps the boundary between a to-be-formed vertical drain region and a to-be-formed adjacent channel region. During subsequent high temperature processing the low diffusion coefficient drain-forming dopant remains concentrated near the top surface of the substrate while other well-forming dopants, including an adjacent channel-forming dopant, which have relatively higher diffusion coefficients, diffuse to deeper regions of the substrate. The slow-diffusing drain-forming dopant retards lateral widening of the channel by the faster-diffusing channel-forming dopant just below the substrate surface to at least the depth of the channel inversion layer formed under the channel surface during device turn on. Retardation of lateral channel growth just below the substrate surface results in an insulated gate device of reduced channel length and improved transconductance. In a preferred embodiment, the slow-diffusing drain-forming dopant is implanted on the substrate surface together with a fast-diffusing drain-forming dopant, and the latter is diffused to a pinch off depth below the substrate surface to counteract pinch off resistance between opposed segments of an adjacent shallow channel-forming well.

IGT and MOSFET devices having reduced channel width

A process for fabricating a power IC structure which includes the following masking steps:

Method of making a power IC structure with enhancement and/or CMOS logic

A p-type region is formed in a semiconductor body by diffusion of aluminum from an aluminum oxide source in an open tube process. Both ceramic aluminum oxide and sapphire sources are described and an inert atmosphere of argon and hydrogen provides stable results. An alternative embodiment provides both the deep diffusion characteristics of aluminum with the high surface concentration of boron by using a boron nitride wafer carrier.

Open tube aluminum oxide disc diffusion

A method for forming a p-conductivity type layer in a semiconductor wafer using aluminum as a diffusion source and which can be carried out in an open diffusion tube is described. A variety of aluminum sources can be employed in an open tube. A stream of essentially oxygen-free inert gas provides transport for the dopant and prevents the entry of potentially contaminating ambient into the tube.

Open tube aluminum diffusion

A guard ring for processing a wafer of semiconductor material by thermal gradient zone melting has a beveled internal wall surface for supporting the wafer therein. The thickness of the guard ring is about twice the thickness of the wafer.

Guard ring for TGZM processing

A method for selectively diffusing a semiconductor body with p-conductivity type impurities utilizing aluminum as a diffusion source and able to be performed in a reuseable open diffusion tube is described. A gas flow is established in the diffusion tube which is essentially an inert gas and includes from one to ten percent oxygen. Simultaneous blanket and selective diffusions may be formed in accordance with this invention by modifying the amount of oxygen in the flow.

Selective open tube aluminum diffusion

A wafer of semiconductor material processed by thermal gradient zone melting is supported by a beveled inner peripheral surface defining an aperture in a guard ring to minimize the distortion of the thermal gradient at the outer peripheral edge surface of the wafer.

Process for thermal gradient zone melting utilizing a beveled wafer and

Aluminum is employed as a carrier metal for antimony in order to N-type dope semiconductor material by temperature gradient zone melting (TGZM) processing.

Droplet migration doping using reactive carriers and dopants

An improved method of initiating the moving of a molten zone of an aluminum rich semiconductor material through a solid body of the same semiconductor material to form a planar region embodies alloying the aluminum metal to the semiconductor material of the surface of the body in contact therewith at a temperature of from 577.degree. to 660.degree. C. The alloying process enables one to migrate two or more intersecting 'wires' simultaneously, as well as three 'wires' intersecting at a common point of origin, through the body.

Semiconductor device manufacture

Disclosed is a method of manufacturing semiconductor devices by thermomigrating impurities through an oxide layer.

Temperature gradient zone melting through an oxide layer

Disclosed is a technique useful in the manufacture of semiconductor devices. A semiconductor wafer is provided and isolation regions are formed therein by the temperature gradient zone melting process. A mask is applied to the surface of the wafer, but the portions of the surface near the isolation regions are left exposed. An etching step follows which removes a small amount of material from the surface of the isolation regions to smooth irregularities formed there during the zone melting process.

Post TGZM surface etch

An improved method of initiating the moving of a molten zone of a metal-rich semiconductor material through a solid body of the same semiconductor material to form a planar region embodies the alloying of the metal to the semiconductor material of the surface of the body in contact therewith. The alloying process enables one to migrate two or more intersecting 'wires' simultaneously, as well as three 'wires' intersecting at a common point of origin, through the body.

Disclosed is a technique useful in the manufacture of semiconductor devices. When a semiconductor device is manufactured by the temperature gradient zone melting process, it is subjected to a short diffusion cycle following thermomigration. The cycle smooths out discontinuities caused by breaks in wire migration and effectively seals and isolates occluded particles of the impurity remaining in the semiconductor body. The cycle is also useful for providing large area doped regions that cannot be formed by wire migration due to constraints on wire direction.

Growing community of inventors

Liverpool, NY, United States of America

Mike F Chang