Siliconix Incorporated

Alpha Omega Semiconductor Inc.

Vishay-siliconix

Other

Silinconix, Inc.

Siliconix Inorporated

Siliconix Incorporation

Mike F Chang

Fwu-Iuan Hshieh

King Owyang

Yueh-Se Ho

Sik Lui

Brian Harold Floyd

Dorman C Pitzer

Anup Bhalla

Hamza Yilmaz

Leeshawn Luo

Richard Kent Williams

Jan Van Der Linde

Jun W Chen

Sze-Hon Kwan

Lixiong Luo

Wei-Bing Chu

Y Mohammed Kasem

Jowei Dun

Lih-Ying Ching

Mohamed N Darwish

Sung-Shan Tai

Wayne Bryan Grabowski

Xiao Meng Zhang

Jun-Wei Chen

David G Grasso

Madhur Bobde

Hong Peng Wang

Daniel Ng

Michael E Cornell

Kuo-In Chen

Moses Ho

Reinhard Zachai

Anthony C Tsui

Mohammed Kasem

Limin Weng

Hans-Jurgen Fusser

Brian Cheung

Chin H Ho

Karen Lee

Agnes Yeung

David Grasso

Juiping Chuang

Jan V Linde

Calvin K Choi

William H Cook

William Cook

Sze H Ng

Hoang Tran

Danny Nim

Min Juang

A semiconductor package includes a leadframe which is cup-shaped and holds a semiconductor die. The leadframe is in electrical contact with a terminal on one side of the die, and the leads of the leadframe are bent in such a way that portions of the leads are coplanar with the other side of the die, which also contains one or more terminals. A plastic capsule is formed around the leadframe and die.

Semiconductor including cup-shaped leadframe packaging techniques

A semiconductor integrated circuit package having a leadframe () that includes a leadframe pad () disposed under a die () and a bonding metal area () that is disposed over at least two adjacent sides of the die. The increase in the bonding metal area () increases the number of interconnections between the metal area () and the die () to reduce the electric resistance and inductance. Furthermore, the surface area of the external terminals radiating from the package's plastic body () is increased if not maximized so that heat can be dissipated quicker and external terminal resistances reduced. The integrated circuit is applicable for MOSFET devices and the bonding metal area () is used for the source terminal (). The bonding metal area may have a 'L' shape, a 'C' shape, a &#x201c;J&#x201d; shape, an &#x201c;I&#x201d; shape or any combination thereof.

Integrated circuit package for semiconductior devices with improved electric resistance and inductance

A semiconductor integrated circuit package having a leadframe () that includes a leadframe pad () disposed under a die () and a bonding metal area () that is disposed over at least two adjacent sides of the die. The increase in the bonding metal area () increases the number of interconnections between the metal area () and the die () to reduce the electric resistance and inductance. Furthermore, the surface area of the external terminals radiating from the package's plastic body () is increased if not maximized so that heat can be dissipated quicker and external terminal resistances reduced. The integrated circuit is applicable for MOSFET devices and the bonding metal area (101) is used for the source terminal (). The bonding metal area may have a 'L' shape, a 'C' shape, a &#x201c;J&#x201d; shape, an &#x201c;I&#x201d; shape or any combination thereof.

Integrated circuit package for semiconductor devices with improved electric resistance and inductance

A transient voltage suppressing (TVS) circuit with uni-directional blocking and symmetric bi-directional blocking capabilities integrated with an electromagnetic interference (EMI) filter supported on a semiconductor substrate of a first conductivity type. The TVS circuit integrated with the EMI filter further includes a ground terminal disposed on the surface for the symmetric bi-directional blocking structure and at the bottom of the semiconductor substrate for the uni-directional blocking structure and an input and an output terminal disposed on a top surface with at least a Zener diode and a plurality of capacitors disposed in the semiconductor substrate to couple the ground terminal to the input and output terminals with a direct capacitive coupling without an intermediate floating body region.

Methods of achieving linear capacitance in symmetrical and asymmetrical EMI filters with TVS

A semiconductor package includes a lead frame having a plurality of leads and a lead frame pad, the lead frame pad including a die coupled thereto, at least one of the plurality of leads having an external portion sloped upwards relative to a bottom surface of the package, metal connectors connecting the die to the plurality of leads, and a resin body encapsulating the die, metal connectors and at least a portion of the lead frame.

Inverted J-lead for power devices

Semiconductor die package including cup-shaped leadframe

Integrated circuit package for semiconductor devices having a reduced leadframe pad and an increased bonding area

A semiconductor package including a relatively thick lead frame having a plurality of leads and a first lead frame pad, the first lead frame pad including a die coupled thereto, bonding wires connecting the die to the plurality of leads, the bonding wires being aluminum, and a resin body encapsulating the die, bonding wires and at least a portion of the lead frame.

Power semiconductor package

Semiconductor assembly with package using cup-shaped lead-frame

Cesium is implanted into the gate oxide layer of a vertical trench-gated MOSFET. The cesium, which is an electropositive material, reduces the threshold voltage of the device and lowers the on-resistance by improving the accumulation region adjacent the bottom of the trench.

Method of making trench-gated MOSFET having cesium gate oxide layer

A trenched field effect transistor suitable especially for low voltage power applications provides low leakage blocking capability due to a gate controlled barrier region between the source region and drain region. Forward conduction occurs through an inversion region between the source region and drain region. Blocking is achieved by a gate controlled depletion barrier. Located between the source and drain regions is a fairly lightly doped body region. The gate electrode, located in a trench, extends through the source and body regions and in some cases into the upper portion of the drain region. The dopant type of the polysilicon gate electrode is the same type as that of the body region. The body region is a relatively thin and lightly doped epitaxial layer grown upon a highly doped low resistivity substrate of opposite conductivity type. In the blocking state the epitaxial body region is depleted due to applied drain-source voltage, hence a punch-through type condition occurs vertically. Lateral gate control increases the effective barrier to the majority carrier flow and reduces leakage current to acceptably low levels.

Method of operation of punch-through field effect transistor

The metal contact to the source and body regions in a vertical planar DMOSFET is formed by fabricating a sidewall spacer on the gate of the MOSFET. With the metal contact self-aligned to the gate in this way, the lateral dimension of each of the cells in the DMOSFET can be significantly reduced without the risk of a short between the contact and the gate, and the packing density of the cells can be increased. In this way, significant reductions in the on-resistance of the device can be achieved.

Method of forming vertical planar DMOSFET with self-aligned contact

In the present method, a semiconductor substrate is provided with an epitaxial layer thereon. A source/drain region is provided in a portion of the epitaxial layer, and a plurality of trenches are etched in the epitaxial layer and extend into the substrate, to define a plurality of mesas. An oxide layer of generally uniform thickness is provided over the mesas and in the trenches, and a polysilicon layer is provided over the oxide layer and is etched so that the oxide layer overlying the mesas is exposed, and the top surface of the polysilicon within the trenches is below the level of the tops of the mesas. A layer of spin-on-glass (SOG) is provided, and the SOG layer and oxide layer are etched substantially to the level of the tops of the mesas, to expose the tops of the mesas and to leave the portions of the SOG over the respective polysilicon portions in the trenches substantially coplaner with the tops of the mesas. A conductive layer is provided over the remaining portions of the SOG layer and the tops of the mesas.

Method of fabricating a field effect transistor

Growing community of inventors

Cupertino, CA, United States of America

Mike F Chang