Intel Corporation

Nvidia Corporation

Mike Cornaby

Shailender Chaudhry

Stephen H Gunther

Stephan Jourdan

Robert J Greiner

Edward Allyn Burton

Darrell D Boggs

Anant S Deval

Ross Segelken

Nathan Daniel Tuck

Nick Fortino

Denis Khartikov

Alok Mooley

Gordon Vreugdenhil

An improved architectural means to address processor cache attacks based on speculative execution defines a new memory type that is both cacheable and inaccessible by speculation. Speculative execution cannot access and expose a memory location that is speculatively inaccessible. Such mechanisms can disqualify certain sensitive data from being exposed through speculative execution. Data which must be protected at a performance cost may be specifically marked. If the processor is told where secrets are stored in memory and is forbidden from speculating on those memory locations, then the processor will ensure the process trying to access those memory locations is privileged to access those locations before reading and caching them. Such countermeasure is effective against attacks that use speculative execution to leak secrets from a processor cache.

Memory type which is cacheable yet inaccessible by speculative instructions

Methods and apparatus to operate various logic blocks of an integrated circuit (IC) at independent voltages are described. In one embodiment, supply of power to one or more domains in an IC is adjusted based on an indication that power consumption by components of the corresponding domain is to be modified. Other embodiments are also described.

Operating integrated circuit logic blocks at independent voltages with single voltage supply

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Hillsboro, OR, United States of America

Mike Cornaby