Equipe Communications Corporation

Cisco Technology, Inc.

Mike A Sluyski

Colin Bell

Brian Branscomb

Glen W Miller

Jim Duda

Markus Weber

In one embodiment, the disclosure includes a network node synchronization system. The system may include a first node. The first node may include a first host card comprising a first (TOD) time of day counter, a first digital signal processor (DSP) comprising a first DSP counter; and a first optical communication device comprising a first DSP communication channel, wherein the first DSP communication channel transports DSP frames. In various embodiments, the DSP is a coherent DSP.

Systems and methods for synchronizing network nodes

The present invention provides a network device including redundant, synchronous central timing subsystems (CTSs) and local timing subsystems (LTSs) including control circuits for automatically selecting between reference signals from both central timing subsystems. Automatically selecting between reference timing signals allows each LTS to quickly switchover from a failing or failed reference timing signal to a good reference timing signal. Quick switchovers prevent data corruption errors that may result during slow switchovers where a failing or failed reference signal is used for a longer period of time prior to the switch over. In addition, since each LTS independently monitors its received reference timing signals, a problem on one reference timing signal is quickly detected by the LTS and the LTS switches over to the good reference timing signal regardless of whether any other LTSs detect a problem with their received reference timing signals. Consequently, each LTS that detects a problem with a timing reference signal may immediately switch over to a good reference signal and not be forced to wait for all LTSs to be switched over.

Network device with local timing systems for automatic selection between redundant, synchronous central timing systems

The present invention provides a network device including redundant, synchronous central timing subsystems (CTSs) each having a voltage controlled timing circuit for receiving a constant master voltage signal and variable slave voltage signal. Each CTS also includes a control logic circuit for selecting the constant master voltage signal for use by the voltage controlled timing circuit when the CTS is master and for selecting the variable slave voltage signal when the CTS is slave. Using a constant master voltage signal eliminates the need for a separate master oscillator in each CTS. Oscillators are typically expensive, consume significant space on the printed circuit board and have location restrictions on where they may be placed on the printed circuit board.

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Maynard, MA, United States of America

Mike A Sluyski