Matsushita Electric Industrial Co., Ltd.

Mikako Yasutome

Masato Suzuki

Minoru Okamoto

Katsuhiko Ueda

Toshihiro Ishikawa

Toshio Sugimura

Hideyo Tsuruta

An interleaving memory system having a first memory device including a 0-bank and a 1-bank for simultaneously outputting data at even-numbered addresses from the 0-bank and data at odd-numbered addresses from the 1-bank, a second memory device including a 0-bank and a 1-bank for simultaneously outputting data at even-numbered addresses from the 0-bank and data at odd-numbered addresses from the 1-bank, and a holding device for holding data from one of the banks of one of the first memory device and the second memory device to delay an output of the data for 1/2 cycle time for sequential addressing. A controller controls first and second selection devices wherein the 0-bank and the 1-bank are alternatively selected when data is outputted either in an ascending order of consecutive addresses from the even-numbered addresses in the first or second memory devices, or in a descending order of consecutive addresses from the odd-numbered addresses in the first or second memory devices. Also, the first holding device and a bank whose output is not held by the first holding device are alternatively selected when data is outputted either in a descending order of consecutive addresses from the even-numbered addresses in the first memory device, or in an ascending order of consecutive addresses from the odd-numbered addresses in the first memory device. The second holding device and a bank whose output is not held by the second holding device are similarly alternatively selected.

Interleaved memory wherein plural memory means comprising plural banks

A data processing apparatus and method for floating point data used in a central processing unit for a digital computer effects the four fundamental arithmetic computations of floating point data and the rounding and normalizing computations. In the case of the floating point addition or subtraction, the mantissa portion of the two floating point data and a generated round addition value are summed using a single adder and, in the case of multiplication, a sum output and a carry output of a multiplying unit and a generated round addition value are added using a single adder, so as to correct the least significant bit of the output of the adder or the round addition value is again added. Since the need of effecting readdition for rounding is small, the average processing step numbers becomes small in comparison with the conventional techniques, and, since the mantissa operation and rounding are effected using the same adder at the same time, less hardware is required.

Floating point data processing apparatus which simultaneously effects

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Moriguchi, Japan

Mikako Yasutome