Analog Devices,inc.

Analog Devices Global

Western Digital Technologies, Inc.

Invensense, Inc.

Analog Devices International Unlimited Company

Analog Devices Global Unlimited Company

Mikael Mortensen

Eric G Nestler

Jeffrey G Bernstein

Robert W Adams

Kim Spetzler Berthelsen

Jacob Midtgaard

J Brian Harrington

Andrew Milia

Khiem Quang Nguyen

Isaac Chase Novet

Grant C Mackey

Ashraf Saad

Sitaram Banda

Michael R Price

Melissa Nolet

Dinesh Matta

Raghu Voleti

An apparatus is provided that includes a memory system that has a memory die that includes a circuit configured to receive at a first input terminal a plurality of bytes comprising an input stream of a first plurality of variable-length encoded symbols, and determine a sequence of symbol byte lengths for each of the first plurality of variable-length encoded symbols.

Regular expression filter for Unicode transformation format strings

Systems and methods are provided for compressing and decompressing data in an ultrasound beamformer. The systems and methods include an encoder for compressing delay data based at least in part on a smoothness of a delay profile, and for compressing apodization data based at least in part on a smoothness of an apodization profile.

Delay and apodization control interface for ultrasound beamformer

Herein disclosed is a system that may be implemented within a headphone to facilitate hearing testing. Implementation of the system in the headphone may include implementation of tone generation circuitry and sound pressure level measurement circuitry being implemented in the headphone limiting the amount of calibration for accurate measurement when performing a hearing test.

Hearing diagnostic system

An apparatus is provided that includes a memory system that includes a memory controller coupled to a storage device capable of streaming data at a first data rate. The memory controller is configured to read a first amount of input data from the storage device at an input data rate equals the first data rate, and provide the first amount of input data at the input data rate to a hardware circuit. The hardware circuit is configured to filter the first amount of input data to provide a second amount of output data at an output data rate, the second amount of output data less than the first amount of input data, the output data rate less than the input data rate. The hardware circuit filters the first amount of input data without repeatedly moving data back and forth between the storage device, a memory buffer, and the hardware circuit.

Hardware accelerator circuits for near storage compute systems

A storage controller includes a plurality of pipeline stages configured to process data. A system clock signal is received that has a system frequency and at least one performance metric is determined for one or more pipeline stages of the plurality of pipeline stages. A first clock signal is generated having a first frequency for operation of a first pipeline stage of the plurality of pipeline stages. Based at least in part on the at least one determined performance metric, a second clock signal is generated having a second frequency for operation of a second pipeline stage of the plurality of pipeline stages. The second frequency is less than the system frequency and may also differ from the first frequency.

Power management for storage controllers

A system for ultrasound beamforming is provided, including a sampled analog beamformer, an array of ultrasound transducers, and a high voltage amplifier coupled to the sampled analog beamformer and the array of ultrasound transducers. The sampled analog beamformer includes a sampled analog filter for filtering an incoming analog signal and adding a fractional delay, and transmitting a filtered analog ultrasound signal. The array of ultrasound transducers further transmits the filtered analog ultrasound signal. The high voltage amplifier drives transducers in the array of ultrasound transducers.

Systems and methods for ultrasound beamforming

Many processes for audio signal processing can benefit from voice activity detection, which aims to detect the presence of speech as opposed to silence or noise. The present disclosure describes, among other things, leveraging energy-based features of voice and insights on first and second formant frequencies of vowels to provide a low-complexity and low-power voice activity detector. A pair of two channels is provided whereby each channel is configured to detect voice activity in respective frequency bands of interest. Simultaneous activity detected in both channels can be a sufficient condition for determining that voice is present. More channels or pairs of channels can be used to detect different types of voices to improve detection and/or to detect voices present in different audio streams.

Low-complexity voice activity detection

Active Noise Cancellation (ANC) systems and methods that reduce latency to improve performance. In certain embodiments the systems sample a noise signal using a sample period to create a stream of digital signal data that is representative of the noise signal. A data transport layer carries the digital signal data to a signal processor. The transport layer temporally organizes the digital signal data to place the digital signal data within an initial phase of a sample period. The remaining phase of the sample period is set to a duration that allows the signal processor to process the digital signal data carried in the initial phase and to output the processed data during the same sample period. In this way, the processing of data occurs within one sample period and the latency is reduced and predictable.

Systems and methods for noise canceling

Sampled analog data are transferred between sampled analog circuits operating on respective local phase clocks which are triggered by a master clock. In response to a first (DATA READY) signal from an upstream sampled analog circuit, the sampled analog data are transferred from an upstream sampled analog circuit to a data transfer circuit. In response to a second (READY FOR DATA) signal from a downstream sampled analog circuit, the sampled data are transferred from the data transfer circuit to the downstream sampled analog circuit. The sampled data are delayed in the data transfer circuit for at least one master clock cycle when the second signal from the downstream sampled analog circuit is received before the first signal is received from the upstream sampled analog circuit.

System and method for sampled analog clock distribution

A sampled analog circuit is divided into at least two segments, each segment receiving sampled analog data and a respective subset of bits of a filter coefficient. The at least two segments can have digital-to-capacitance circuits with substantially identical ranges of capacitance values. One or more outputs from the segments can be scaled to reflect a position of the subset of bits in the bits of the filter coefficient, and thereafter added in the analog domain to produce a filtered output signal that may then be digitized. Alternatively, the outputs from the segments may be digitized before being scaled and/or added in the digital domain.

High precision sampled analog circuits

A microprocessor circuit may include a software programmable microprocessor core and a data memory accessible via a data memory bus. The data memory may include sets of configuration data structured according to respective predetermined data structure specifications for configurable math hardware accelerators, and sets of input data for configurable math hardware accelerators, each configured to apply a predetermined signal processing function to the set of input data according to received configuration data. A configuration controller is coupled to the data memory via the data memory bus and to the configurable math hardware accelerators. The configuration controller may fetch the configuration data for each math hardware accelerator from the data memory and translate the configuration data. The configuration controller may transmit each set of configuration data to the corresponding configurable math hardware accelerator and write the configuration data to configuration registers of the math hardware accelerator.

Hardware accelerator configuration by a translation of configuration data

The present invention relates in one aspect to an audio amplification circuit comprising an input terminal for receipt of an input signal from a transducer. A signal processor is operatively coupled to the input terminal for receipt and processing of the input signal to generate a processed digital audio signal in accordance with a programmable configuration setting of the signal processor. A serial data transmission interface is configured for receipt of the processed digital audio signal and supply of a corresponding digital audio stream at an output terminal of the integrated audio amplification circuit. A serial data receipt interface is operatively coupled to an externally accessible configuration terminal of the integrated audio amplification circuit and a controller is configured to adjust one of the programmable configuration setting of the signal processor and a format of a digital audio stream in accordance with first configuration data received through the serial data receipt interface. The controller is in a first state is responsive to a logic state of the externally accessible configuration terminal to control the format of the digital audio stream or the programmable configuration setting. In a second state, the controller is configured for receipt and reading of the first configuration data through the externally accessible configuration terminal and the serial data receipt interface.

Integrated audio amplification circuit with multi-functional external terminals

A datapath circuit may include a digital multiply and accumulate circuit (MAC) and a digital hardware calculator for parallel computation. The digital hardware calculator and the MAC may be coupled to an input memory element for receipt of input operands. The MAC may include a digital multiplier structure with partial product generators coupled to an adder to multiply a first and second input operands and generate a multiplication result. The digital hardware calculator may include a first look-up table coupled between a calculator input and a calculator output register. The first look-up table may include table entry values mapped to corresponding math function results in accordance with a first predetermined mathematical function. The digital hardware calculator may be configured to calculate, based on the first look-up table, a computationally hard mathematical function such as a logarithm function, an exponential function, a division function and a square root function.

Growing community of inventors

Cambridge, MA, United States of America

Mikael Mortensen