Telefonaktiebolaget Lm Ericsson (publ)

Mikael Lindberg

Ulf Peter Hansson

Stefan Gustafsson

Mats Ernkell

Stefan Davidsson

A semiconductor arrangement is provided for generating a predetermined time delay. Two clocks are connected to two parallel, redundant semi-conductor circuits emitting clock signals from multiplexers. The redundant circuits receive delayed clock signals from one of the clocks, and from the other clock, clock signals that are delayed in adjustable delay circuits to be phased in with the clock signals from the first clock. A number of delay elements and a first reference number of delay elements, providing a predetermined delay time, are connected in a reference delay circuit. A quotient of the two numbers is stored. One of the semi-conductor circuits is replaced by an alternative semi-conductor circuit, the reference delay circuit of which is set on the predetermined delay time, corresponding to a second reference number of delay elements. An adjustable delay circuit is set on the same delay time as the replaced semi-conductor circuit by means of the second reference number and the quotient.

Apparatus and method for generating a predetermined time delay in a semiconductor circuit

In a general switch, a word oriented switch and a bit oriented switch are connected such that a common input signal included data appearing in time slots is provided to both switches. The general switch further includes a device for establishing, for each one of a number of outgoing time slots, at least one of a first connection path through the word oriented switch and a second connection through the bit oriented switch, and a device for selecting, for each outgoing time slot, data from an established one of the connection path. For each outgoing time slot, only one of the connection paths is established and the selecting device selects data from the established connection path.

General switch and a switching method

A method and system for testing a memory in operation. A storage unit is used to temporarily free one memory location in the memory, making it possible to check this memory location for bit errors. Data intended for the selected memory location is stored in the storage unit, and instead a test pattern is written into the memory location to be tested and read out again, all in coordination with the normal operation of the memory. If the pattern read from the test location does not match the written test pattern, an alarm is raised.

Memory supervision

In a switch structure for circuit switching, part of the space switch functionality of a time-space (TS) switch core is broken out and arranged in groups of switch adapter boards, and the TS-switch core itself is divided into a matrix of smaller and independent TS-modules that are associated with the switch adapter boards. Each group of switch adapter boards is co-operating with a predetermined row of TS-modules in the matrix for input of data to the TS-modules in that row, and with a predetermined column of TS-modules in the matrix for output of data from the TS-modules of that column. In this way, it is possible to implement the switch structure into a number of subracks with a reasonable number of interconnections between different subracks, thus obtaining a truly modular TS-switch structure.

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Täby, Sweden

Mikael Lindberg