Nokia Corporation

St-ericsson Sa

Mika Salmi

Pauli Mikael Seppinen

Juha Samuel Hallivuori

Janne Peltonen

Seppo Rosnell

Simo Murtojärvi

Mikael Svard

Antti Rauhala

Jens Rosendahl

Ville Ruuska

A system () comprises a first circuit () for transmitting information to a second circuit (). The first circuit () comprises a signal generator () arranged to generate a signal () for transmission to the second circuit (). The signal () has a first state for causing the second circuit () to perform a first operation and a second state for causing the second circuit () to perform a second operation. The signal generator () comprises means to modulate the generated signal () during a data burst period () to encode data into the generated signal (). The data burst period () occurs within a period in which the generated signal () is in the second state. The signal () is modulated such that the encoded data is distinguishable from the generated signal (). In an embodiment, a data burst period () comprises a plurality of data periods () during which the state of the signal is representative of the data encoded in the signal (). The data periods () may be separated by padding periods () during which the signal () is in the second state, The data burst period may be initiated following a delay after the signal changes from being in the first state to being in the second state.

Clocking signal control

The frequency response of a digital filter, such as a pre-emphasis filter in a signal transmitter having a phase-locked loop, is adjusted using interpolation of the filter coefficients, enabling sets of filter coefficients to be pre-computed or generated as needed in the transmitter. The phase error behavior of the digital filter can be significantly improved.

Interpolation of filter coefficients

A transmitter for generating modulated signals is shown, wherein in a first-type operating mode, a first digital signal is input into a digital-to-analog converter to obtain a first analog signal that is input into a first-type unit, in which a first-type modulated signal is generated in dependence on at least the first analog signal; and wherein in a second-type operating mode, a second digital signal is input into the digital-to-analog converter to obtain a second analog signal that is input into a second-type unit, in which a second-type modulated signal is generated in dependence on at least the second analog signal. Correspondingly, a wireless communication device is shown, as well as a base station, a module in a wireless communication device, a module in a base station, an integrated circuit, a method, a computer program and a computer program product.

Reuse of digital-to-analog converters in a multi-mode transmitter

This invention describes a method for a component/system level design of an adaptive radio receiver in electronic communication devices (e.g., mobile phones) by providing an automatic digital tuning of a voltage controlled oscillator of a phase locked loop (PLL) instead of a prior-art pre-calibration. A normal PLL for frequency locking is used which does not need any additional pre-calibration blocks to account for different temperatures or any other extreme conditions. If the current switch setting does not allow the locking, i.e., the VCO output signal frequency is still far away from a reference frequency, the PLL 'coarse' tuning will cause the switch condition to change and bring the frequency within a reasonable range using an additional phase detector PDloop.

Digital tuning of a voltage controlled oscillator of a phase locked loop

A resampling technique is used to reduce the noise and improve the signal quality in the output of a prescaler circuit ( ). The resampling of the output of a last frequency divider stage is accomplished using at least one flip/flop (FF) (e.g., a D-type FF ) that is clocked by a signal obtained from the input of the prescaler. This reduces or eliminates the noise caused by edge jitter in the output of the prescaler, as well as the effect of spurious signals generated by the prescaler. These teachings can be used in integer N PLLs and in fractional N PLLs, as well as in single and programmable dual or multi-modulus prescalers. Using this technique the current consumption of the prescaler frequency dividers ( ) need not be increased in an effort to reduce the prescaler noise, thereby conserving current in battery powered and other applications.

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Turku, Finland

Mika Salmi