California Institute of Technology

Mika Nystrom

Rajit Manohar

Alain J Martin

Andrew M Lines

Uri V Cummings

An asynchronous processor having pipelined instruction fetching and execution to implement concurrent execution of instructions by two or more execution units. A writeback unit is connected to execution units and memory units to control information updates and to handle precise exception. A pipelined completion mechanism can be implemented to improve the throughput.

Pipelined asynchronous processing

Exception handling systems and techniques for handling exceptions and sequencing conflicts in an asynchronous processor. Two designated queues are used to respectively keep program counter values of instructions and the assignments of the execution units for executing the instructions according to the program order. An asynchronous circuit is coupled between the program counter unit and the write-back unit of the processor to provide asynchronous communications.

Growing community of inventors

Pasadena, CA, United States of America

Mika Nystrom