California Institute of Technology

Intel Corporation

Mika Nystroem

Alain J Martin

Robert G Southworth

Mark A Bordogna

Jonathan A Dama

Janardhan H Satyanarayana

Wonjin Jang

Larry N Wakeman

Arvind Srinivasan

Rajit Manohar

David Arditti Ilitzky

Andrew M Lines

Uri V Cummings

Karl S Papadantonakis

Catherine G Wong

Examples describe use of multiple meta-data delivery schemes to provide tags that describe packets to an egress port group. A tag, that is smaller than a packet, can be associated with a packet. The tag can be stored in a memory, as a group with other tags, and the tag can be delivered to a queue associated with an egress port. Packets received at an ingress port can be as non-interleaved to reduce underrun and providing cut-through to an egress port. A shared memory can be allocated to store packets received at a single ingress port or shared to store packets from multiple ingress ports.

Multi-path packet descriptor delivery scheme

Technologies for high-precision timestamping of data packets is disclosed. Several sources of errors that may arise when timestamping the arrival or sending of data packets may be determined and corrected, including variable latencies, semi-static latencies, and fixed latencies. In the illustrative embodiment, a variable latency may arise due to a phase difference between a clock of a network interface card and a system clock. When a trigger pattern is detected, such as the start of a data packet, a trigger may be sent from a circuit synchronized to the clock of the network interface card to a circuit synchronized to the system clock. The phase difference between the edge of the clock on the network interface card and the edge of the clock of the system clock leads to an error in the timestamp value. Determining the phase difference allows for the error in the timestamp value to be corrected.

Technologies for high-precision timestamping of packets

The invention provides circuits that are tolerant to soft errors, such as a single event upset (SEU). The circuits have a chain of permitted state changes. Redundant elements, including redundant literals and assignments, are designed and implemented in the circuit. The design is such that a disruption or change of state on a single element by an SEU will not change the state flow of a circuit or lead to impermissible state changes. In one embodiment, the invention is implemented in quasi-delay-insensitive (QDI) asynchronous circuits.

Method and apparatus for providing SEU-tolerant circuits

The present invention is a systematic and data-driven-decomposition (DDD) method and apparatus for use in VLSI synthesis. The invention decomposes a high level program circuit description into a collection of small and highly concurrent modules that can be implemented directly into transistor networks. This enables an automatic implementation of a decomposition process currently done by hand. Unlike prior art syntax-based decompositions, the method of the present invention examines data dependencies in the process' computation, and then attempts to eliminate unnecessary synchronization in the system. In one embodiment, the method comprises: a conversion to convert the input program into an intermediate Dynamic Single Assignment (DSA) form, a projection process to decompose the intermediate DSA into smaller concurrent processes, and a clustering process that optimally groups small concurrent processes to make up the final decomposition. Another embodiment is a decomposition, projection, and clustering tool implemented in computer program codes.

Method for the synthesis of VLSI systems based on data-driven decomposition

Systems and methods for mitigating the effects of soft errors in asynchronous digital circuits. Circuits are constructed using stages comprising doubled logic elements which are connected to c-elements that compare the output states of the double logic elements. The inputs of logic elements in a stage are inhibited from changing until the outputs of the c-elements of that stage are enabled. The c-elements inhibit the propagation of a soft error by halting the operation of the circuit until the temporary effects of the soft error pass.

Duplicated double checking production rule set for fault-tolerant electronics

An asynchronous processor having pipelined instruction fetching and execution to implement concurrent execution of instructions by two or more execution units. A writeback unit is connected to execution units and memory units to control information updates and to handle precise exception. A pipelined completion mechanism can be implemented to improve the throughput.

Growing community of inventors

Pasadena, CA, United States of America

Mika Nystroem