Tokyo Electron Limited

Miho Jomen

Tadahiro Ishizaka

Kenji Suzuki

Shigeru Mizuno

Jonathan Rullan

Atsushi Gomi

Yasushi Mizusawa

Frank M Cerio, Jr

A method is provided for controlling copper agglomeration on a substrate and for forming void-free bulk copper metal filling of recessed features in integrated circuits. In one embodiment, the method includes providing a substrate having a topography including a top surface and at least one recessed feature comprising at least a sidewall surface and a bottom surface, depositing a barrier film on the substrate topography, and depositing a metal-containing wetting film on the barrier film. The method further includes physical vapor depositing copper metal on the metal-containing wetting film, where the substrate temperature is sufficiently high to form a smooth copper metal seed layer on the metal-containing wetting film. Void-free bulk copper metal may be plated in the at least one recessed feature.

Void-free copper filling of recessed features using a smooth non-agglomerated copper seed layer

A method is provided for void-free copper (Cu) filling of recessed features in a semiconductor device. The method includes providing a patterned substrate containing a recessed feature, depositing a barrier film on the patterned substrate, including in the recessed feature, depositing a Ru metal film on the barrier film, and depositing a discontinuous Cu seed layer on the Ru metal film, where the Cu seed layer partially covers the Ru metal film in the recessed feature. The method further includes exposing the substrate to an oxidation source gas that oxidizes the Cu seed layer and the portion of the Ru metal film not covered by the Cu seed layer, heat-treating the oxidized Cu seed layer and the oxidized Ru metal film under high vacuum conditions or in the presence of an inert gas to activate the oxidized Ru metal film for Cu plating, and filling the recessed feature with bulk Cu metal. The exposure to the oxidation source gas can be an air exposure commonly encountered in semiconductor device manufacturing prior to Cu plating.

Void-free copper filling of recessed features for semiconductor devices

A method is provided for integrating cobalt nitride cap layers into manufacturing of semiconductor devices to improve electromigration and stress migration in copper (Cu) metal. One embodiment includes providing a patterned substrate containing a recessed feature formed in a low-k material and a first metallization layer at the bottom of the feature, forming a cobalt nitride cap layer on the first metallization layer, depositing a barrier layer in the recessed feature, including on the low-k dielectric material and on the first cobalt metal cap layer, and filling the recessed feature with Cu metal. Another embodiment includes providing a patterned substrate having a substantially planar surface with Cu paths and low-k dielectric regions, and selectively forming a cobalt nitride cap layer on the Cu paths relative to the low-k dielectric regions.

Method for forming cobalt nitride cap layers

A method for integrating ruthenium (Ru) metal cap layers and modified Ru metal cap layers into copper (Cu) metallization of semiconductor devices to improve electromigration (EM) and stress migration (SM) in bulk Cu metal. In one embodiment, the method includes providing a planarized patterned substrate containing a Cu metal surface and a dielectric layer surface, depositing first Ru metal on the Cu metal surface, and depositing additional Ru metal on the dielectric layer surface, where the amount of the additional Ru metal is less than the amount of the first Ru metal. The method further includes at least substantially removing the additional Ru metal from the dielectric layer surface to improve the selective formation of a Ru metal cap layer on the Cu metal surface. Other embodiments further include incorporating one or more types of modifier elements into the dielectric layer surface, the Cu metal surface, the Ru metal cap layer, or a combination thereof.

Method for forming a ruthenium metal cap layer

A method for integrating low-temperature selective Ru metal deposition into manufacturing of semiconductor devices to improve electromigration and stress migration in bulk Cu metal. The method includes providing a patterned substrate containing a recessed feature in a dielectric layer, where the recessed feature is at least substantially filled with planarized bulk Cu metal, heat-treating the bulk Cu metal and the dielectric layer in the presence of H, N, or NH, or a combination thereof, and selectively depositing a Ru metal film on the heat-treated planarized bulk Cu metal.

Method for integrating selective low-temperature ruthenium deposition into copper metallization of a semiconductor device

A method is provided for integrating cobalt tungsten cap layers into manufacturing of semiconductor devices to improve electromigration and stress migration in copper (Cu) metal. One embodiment includes providing a patterned substrate containing a recessed feature formed in a low-k material and a first metallization layer at the bottom of the feature, forming a cobalt tungsten cap layer on the first metallization layer, depositing a barrier layer in the recessed feature, including on the low-k dielectric material and on the first cobalt metal cap layer, and filling the recessed feature with Cu metal. Another embodiment includes providing a patterned substrate having a substantially planar surface with Cu paths and low-k regions, and forming a cobalt tungsten cap layer on the Cu paths.

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Watervliet, NY, United States of America

Miho Jomen