Texas Instruments Corporation

Mihir Narendra Mody

Niraj Nandan

Hetul Sanghvi

Rajasekhar Reddy Allu

Sriramakrishnan Govindarajan

Shashank Dabral

Kedar Satish Chitnis

Gregory Raymond Shurtz

Jason A T Jones

Chaitanya Satish Ghone

Brian Okchon Chae

Gang Hua

Hrushikesh Tukaram Garud

Kishon Vijay Abraham Israel Vijayponraj

Anthony J Lell

Anish Reghunath

Prithvi Shankar Yeyyadi Anantha

Soyeb Noormohammed Nagori

Rajat Sagar

Shailesh Ganapat Ghotgalkar

Hideo Tamama

Michael Peter Lachmayr

Manu Mathew

Denis R Beaudoin

Aishwarya Dubey

Mayank Mangla

Brijesh Rameshbhai Jadav

Veeramanikandan Raju

Rahul Gulati

Charles Lance Fuoco

Amritpal Singh Mundra

Shyam Jagannathan

Sujith Shivalingappa

Prashant Dinkar Karandikar

Vasant Easwaran

Nainala Vyagrheswarudu

Minhua Zhou

Deepak Kumar Poddar

Dipan Kumar Mandal

Mahesh Madhukar Mehendale

Ranga Ramanujam Srinivasan

Manoj Koul

Jesse Gregory Villarreal, Jr

Hemant Hariyani

Subrangshu Kumar Das

Joseph Meehan

Pandy Kalimuthu

Hemant Vijay Kumar Hariyani

Ajay Jayaraj

Anand Balagopalakrishnan

Jayant Thakur

Pramod Kumar Swami

Vikram Vijayanbabu Appia

Donald Edward Steiss

Gary A Cooper

Kumar Arrakutti Desappan

Pavan Venkata Shastry

William A Mills

Ankit Ajmani

Santhanakrishnan Badri Narayanan

Vignesh Raghavendra

Ankur Ankur

Jason T Jones

Daniel Brad Wu

William Cronin Wallace

Jing-Fei Ren

Yashwant Dutt

Denis Roland Beaudoin

Sanand Prasad

Jonathan Elliot Bergsagel

Mark Adrian Bryans

Vikram VijayanBabu Appia

Lucas Carl Weaver

Vijayavardhan Baireddy

Abhishek Shankar

Kapil Ahuja

Cory Dean Stewart

Mohammad Asif Farooqui

Martin Jeffrey Ambrose

Vipul Paladiya

Prithvi Y A Shankar

Hetul Sanghavi

Bradley Douglas Cobb

Sriramakrishan Govindarajan

Vijaya Rama Raju Kanumuri

Arthur John Redfern

Ajit Venkat Rao

Samuel Paul Visalli

Jason A Jones

David E Smith

Piyali Goswami

Mel Alan Phipps

Kumar Desappan

Tarek Aziz Lahlou

Anshu Jain

Rishabh Garg

Srirama Krishnan Govindarajan

M V Ratna Reddy

A hub that receives sensor data streams and then distributes the data streams to the various systems that use the sensor data. A demultiplexer (demux) receives the streams, filters out undesired streams and provides desired streams to the proper multiplexer (mux) or muxes of a series of muxes. Each mux combines received streams and provides an output stream to a respective formatter or output block. The formatter or output block is configured based on the destination of the mux output stream, such as an image signal processor, a processor, memory or external transmission. The output block reformats the received stream to a format appropriate for the recipient and then provides the reformatted stream to that recipient.

Flexible hub for handling multi-sensor data

Various examples disclosed herein relate to deterministically controlling interconnect operations to provide dynamic power gating for a system. In an example, a microcontroller unit (MCU) is provided that includes a group of processing devices, a group of target resources, interconnect circuitry, and clock control circuitry. The interconnect circuitry connects the group of processing devices to the group of target resources. The clock control circuitry is coupled to the interconnect circuitry. The clock control circuitry is configured to identify an upcoming occurrence of a communication between a pair of devices comprised of one of the processing devices and one of the target resources, and prior to the occurrence of the communication, enable a clock associated with a path through the interconnect circuitry between the pair of devices.

Dynamic power gating using deterministic interconnect

An example apparatus includes a read queue to store a first read request to access a first storage, sequencing circuitry coupled to the read queue, and prioritization circuitry coupled to the sequencing circuitry and coupled to the first storage and a second storage via a shared bus. The example sequencing circuitry is to sequence a portion of a second request to access the second storage to be interleaved with a wait interval of the first read request, the second request queued after the first read request. Additionally, the example prioritization circuitry is to generate a first transaction to access the first storage over the shared bus and a second transaction to access the second storage over the shared bus concurrently with the first transaction, the first transaction based on the first read request, the second transaction based on the second request.

Methods, apparatus, and articles of manufacture to interleave data accesses for improved throughput

This disclosure relates to various implementations an embedded computing system. The embedded computing system comprises a hardware accelerator (HWA) thread user and a second HWA thread user that creates and sends out message requests. The HWA thread user and the second HWA thread user is communication with a microcontroller (MCU) subsystem. The embedded computing system also comprises a first inter-processor communication (IPC) interface between the HWA thread user and the MCU subsystem and a second IPC interface between the second HWA thread user and the MCU subsystem, where the first IPC interface is isolated from the second IPC interface. The MCU subsystem is also in communication with a first domain specific HWA and a second domain specific HWA.

Safe, secure, virtualized, domain specific hardware accelerator

Techniques for executing machine learning (ML) models including receiving an indication to run an ML model on a processing core; receiving a static memory allocation for running the ML model on the processing core; determining that a layer of the ML model uses more memory than the static memory allocated; transmitting, to a shared memory, a memory request for blocks of the shared memory; receiving an allocation of the requested blocks; running the layer of the ML model using the static memory and the range of memory addresses; and outputting results of running the layer of the ML model.

Memory sharing for machine learning processing

A technique for rendering an under-vehicle view including obtaining a first location of a vehicle, the vehicle having a set of cameras disposed about the vehicle, capturing a set of images; storing images of the set of images in a memory, wherein the images are associated with a time the images were captured, moving the vehicle to a second location, obtaining the second location of the vehicle, determining an amount of time for moving the vehicle from the first location to the second location, generating a set of motion data, the motion data indicating a relationship between the second location of the vehicle and the first location of the vehicle, obtaining one or more stored images from the memory based on the determined amount of time, rendering a view under the vehicle based on the one or more stored images and set of motion data, and outputting the rendered view.

Below vehicle rendering for surround view systems

In described examples, a device includes a transmitter, a receiver, and a control circuit. The transmitter transmits a clock signal, and the receiver receives a response signal. The control circuit is coupled to the transmitter and the receiver. The control circuit causes the transmitter to transmit a first clock signal with a first clock period, and to transmit a second clock signal with a second clock period greater than the first clock period. The control circuit determines whether a first pattern of a signal responsive to the first clock signal is the same as a second pattern of a signal responsive to the second clock period. If the patterns are the same, the control circuit delays the clock signal with a delay responsive to the first clock period to generate a delayed clock signal. The receiver samples response signals using the delayed clock signal during normal operation of the device.

Communication interface with calibrating delay circuit

A system-on-chip (SoC) may be configured to enable a Multi-Chip Daisy Chain Topology using peripheral component interface express (PCIe). The SoC may include a processor, a local memory, a root complex operably connected to the processor and the local memory, and a multi-function endpoint controller. The root complex may obtain forwarding information to configure routing of transactions to one or more PCIe endpoint functions or to the local memory. The root complex may initialize, based on the forwarding information, access between a host and the one or more PCIe endpoint functions. The multi-function endpoint controller may obtain a descriptor and endpoint information to configure outbound portals for transactions to at least one remote host. The multi-function endpoint controller may establish a communication path between the host and a function out of a plurality of functions.

Enabling a multi-chip daisy chain topology using peripheral component interconnect express (PCIe)

Examples systems are provided for isolating transactions originating from different types of applications, including systems for providing such isolation on an inbound side and systems for providing such isolation on an outbound side, as well as end-to-end isolation systems. Such systems may be implemented in a peripheral component interconnect express (PCIe) environment. On an outbound side, a first interconnect receives transactions having different attributes indicating different application origins, respectively, and selects different pathways for the transactions based on their respective attributes. On an inbound side, a second interconnect selects different pathways for the transactions based on their respective attributes. Thus, transactions originating from safety and non-safety applications may be kept isolated as they are routed, and a non-safety transaction may be restricted from accessing certain portions of memory.

End-to-end isolation over PCIe

Several systems and methods for processing of video frames based on one or more video formats are disclosed. In an embodiment, a video processing system comprises a memory and a video engine. The memory stores a plurality of video frames, a primary set of instructions and a plurality of secondary sets of processing instructions. Each secondary set of processing instructions is associated with a video format. The video engine is loaded with the primary set of instructions and is configured to fetch one or more video frames and a secondary set of processing instructions from the memory based on the loaded primary set of instructions. The fetched secondary set of processing instructions corresponds to a video format determined for processing of the one or more video frames. The video engine performs processing of the one or more video frames based on the secondary set of processing instructions.

Systems and methods for video processing

In some examples, a method comprises receiving pixel data from an image capture device having a color filter, wherein the pixel data represents a portion of an image. The method further includes performing wavelet decomposition on the pixel data to produce decomposed pixel data and determining a local intensity of the pixel data. The method also includes determining a noise threshold value based on the local intensity and a noise intensity function that is based on the color filter; determining a noise value for the pixel data based on the decomposed pixel data and the noise threshold value; and correcting the pixel data based on the noise value to produce an output image.

Noise estimation using user-configurable information

A method of de-blocking filtering a processed video is provided. The processed video includes a plurality of blocks and each block includes a plurality of sub-blocks. A current block of the plurality of blocks includes vertical edges and horizontal edges. The processed video further includes a set of control parameters and reconstructed pixels corresponding to the current block. A boundary strength index is estimated at the vertical edges and at the horizontal edges of the current block. The set of control parameters, the reconstructed pixels corresponding to the current block and partially filtered pixels corresponding to a set of adjacent sub-blocks are loaded. The vertical edges and the horizontal edges of the current block are filtered based on the boundary strength index and the set of control parameters such that a vertical edge of the current block is filtered before filtering at least one horizontal edge of the current block.

De-blocking filter for video coding

Arbitration and interleaving are performed with respect to memory requests in a memory controller that includes a set of interfaces, each configured to be coupled to a respective one of multiple external requestors, in which each interface receives memory requests from its associated external requestor. The memory controller further includes multiple sets of memory channel queues, one set for each interface, and multiple requestor arbitration modules, each associated with and coupled to a respective one of the multiple sets of memory channels. The memory controller further includes an interconnect coupled to the multiple requestor arbitration modules. The interconnect includes multiple external memory arbitration modules. Each of the requestor arbitration modules applies an arbitration algorithm to arbitrate among the memory requests in the associated set of memory channel queues. Each of the external memory arbitration modules also applies an arbitration algorithm to arbitrate among memory requests presented by the requestor arbitration modules.

Multichannel memory arbitration and interleaving scheme

Described examples include an integrated circuit including a vector multiply unit including a plurality of multiply/accumulate nodes, in which the vector multiply unit is operable to provide an output from the multiply/accumulate nodes, a first data feeder operable to provide first data to the vector multiply unit in vector format, and a second data feeder operable to provide second data to the vector multiply unit in vector format.

Methods and apparatus for matrix processing in a convolutional neural network

Various examples disclosed herein relate to trimming of system elements to prepare the elements for execution of boot code and application code. In an example embodiment, a system is provided. The system includes memory access circuitry and processing circuitry coupled to the memory access circuitry. The memory access circuitry is configured to receive a read request corresponding to a set of instructions for execution by processing circuitry stored in non-volatile memory, determine whether to preempt current access to the non-volatile memory corresponding to one or more access requests in favor of the read request based on a priority of the read request relative to the one or more access requests, obtain the set of instructions from the non-volatile memory, and supply the set of instructions to the processing circuitry. The processing circuitry executes the set of instructions.

Flash memory access scheduling

Growing community of inventors

Bengaluru, India

Mihir Narendra Mody