International Business Machines Corporation

Mihir Choudhury

Ruchir Puri

Robert Lowell Kanzelman

Sharad C Sundararajan

Alexander Ivrii

David John Geiger

Ayesha Akhter

Subhendu Roy

Maja Vukovic

Jason Raymond Baumgartner

Anup Kalia

Elizabeth Daly

Alexander Joel Suess

John Joseph Rofrano

Jin Xiao

Oznur Alkan

Andrew James Sullivan

Atin Sood

Josiah Hamilton

Lambert Pouguem Wassi

An example system includes a processor to receive a high-level design representation of a system architecture. The processor can synthesize a logic design and generate an associated synthesis history based on the high-level hardware design representation. The processor can then execute an equivalence check between the high-level design and the synthesized logic design based on the generated synthesis history.

Equivalence checking of synthesized logic designs using generated synthesis history

Techniques regarding discovering configuration information for one or more computer applications are provided. For example, one or more embodiments described herein can comprise a system, which can comprise a memory that can store computer executable components. The system can also comprise a processor, operably coupled to the memory, and that can execute the computer executable components stored in the memory. The computer executable components can comprise a configuration component that can discover configuration information associated with a containerized computer application. The configuration information can be characterized by a set of environment attributes extracted by querying a source code of the containerized computer application.

Configuration discovery of computer applications

In an approach for optimization of integer arithmetic expressions implemented as a Boolean logic circuit, a processor converts arithmetic operators in an arithmetic expression into adders. A processor identifies a topological order of the adders. A processor merges the adders based on the topological order into a multi-operand adder. A processor converts the multi-operand adder to a compressor tree and a two-operand adder. A processor performs the arithmetic expression based on the converted multi-operand adder.

Optimization of arithmetic expressions

Mechanisms are provided for synthesizing a computer implemented neural network. An initially trained neural network is received and modified by introducing a new hidden layer of neurons and new connections that connect the new hidden layer of neurons to an output layer and a previous layer of neurons previously directly connected to the output layer of neurons to generate a modified neural network. The modified neural network is trained through one or more epochs of machine learning to generate modified weight values for the new connections and the new connections are pruned based on the modified weight values to remove a subset of the new connections and leaving remaining connections in the modified neural network. A merge operation is performed on the remaining connections in the modified neural network to generate a custom convolution filter and modified neural network. The modified neural network is then retrained for deployment.

Building of custom convolution filter for a neural network using an automated evolutionary process

Technical solutions are described herein for fabrication of a chip with optimized chip design during the logical synthesis phase of the fabrication. An example method includes optimizing, by a physical synthesis system, a chip design for a chip to be fabricated, the optimization performed according to a first performance metric for the entire chip. The method further includes receiving, by the physical synthesis system, a feedback input comprising a region of the chip and a second performance metric associated with the region. The method further includes modifying, by the physical synthesis system, the chip design by optimizing the region of the chip according to the second performance metric. The method further includes sending, by the physical synthesis system, the modified chip design for fabrication of the chip.

Automated region based optimization of chip manufacture

Techniques for transforming input operands to reduce overhead for implementing addition operations in hardware are provided. In one aspect, a method for transforming input operands of an adder includes the steps of: receiving a bit array of the input operands; replacing a duplicate signal (e.g., a signal that occurs twice) for a given bit k in the bit array with a single signal at bit k+1; reducing a number of occurrences of the signal on adjacent bits of the input operand, wherein by way of the replacing and reducing a transformed bit array is formed; and providing the transformed bit array to the adder.

Transformation on input operands to reduce hardware overhead for implementing addition

A method for automated synthesis of a parallel prefix device includes determining structural constraints for a given parallel prefix device; generating a plurality of candidate prefix graphs for the parallel prefix device by performing a search of possible prefix graphs meeting the constraints; performing physical synthesis of each of the plurality of candidate prefix graphs to generate performance information for each candidate prefix graph; and determining one or more of the plurality of candidate prefix graphs that meet performance criteria for incorporation into the parallel prefix device.

Automated synthesis of high-performance two operand binary parallel prefix adder

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New York, NY, United States of America

Mihir Choudhury