Intel Corporation

Micron Technology Incorporated

Mihir Bohra

Tarun Mudgal

Andrea Redaelli

Maneesh Mishra

D Ross Economy

Nathan A Wilkerson

Some embodiments include a method of forming an arrangement. A first tier is formed to include CMOS circuitry. A second tier is formed to include an assembly which has first and second sets of memory cells on opposing sides of a coupling region. A support material is adjacent the first and second sets of the memory cells, and an intervening material is adjacent the support material. The support material has a different composition than the intervening material. A conductive interconnect extends through the intervening material. An upper surface of the assembly is polished to reduce an overall height of the assembly. The support material provides support during the polishing to protect the memory cells from being eroded during the polishing. The conductive interconnect of the second tier is coupled with the CMOS circuitry of the first tier. Some embodiments include multitier arrangements.

Multitier arrangements of integrated devices, and methods of protecting memory cells during polishing

A memory device includes a plurality of memory cells, a first nonconductive separator material separating the memory cells and having a word line end and bit line end, a metal via separated from the plurality of memory cells by a second nonconductive separator material, and metal bit line electrically connecting the metal via with the plurality of memory cells. The memory cells include a phase change material layer, a first electrode layer adjacent to the phase change material layer and having a phase change material layer side oriented toward the phase change material layer and a bit line side opposite the phase change material layer side, a metal silicon nitride layer on a surface of the bit line side of the first electrode layer. A bit line end surface of the first nonconductive separator material is at least partially free of contact with the metal silicon nitride layer.

Phase change memory devices with enhanced vias

A phase change memory structure () can include a memory cell, a dielectric material () adjacent to the memory cell, and a bit line. The memory cell can include a phase change material layer () and a top electrode layer () above the phase change material layer. The dielectric material can have a top surface () that is higher than a top surface () of the top electrode layer. The bit line () can have a non-flat bottom surface that contacts the top surface of the dielectric material and protrudes down from the top surface of the dielectric material to a top surface of the memory cell.

Phase change memory structures

A nonvolatile memory device includes a metal silicon nitride layer on a three-dimensional (3D) crosspoint architecture, where the metal silicon nitride layer is in the memory array processing. The metal silicon nitride layer is patterned in accordance with the memory array structure, rather than being an underlying layer for a metal layer. The metal layer provides bitline or wordline select paths, and can connect to a via in parallel with the memory array stack. The metal silicon nitride layer is between the metal layer and the memory array, and is not present over the via.

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Boise, ID, United States of America

Mihir Bohra