Teledyne Scientific and Imaging, LLC

Continental Autonomous Mobility US, LLC

Mihail Milkov

Patrick Gilliland

Patrick B Gilliland

Vincent Douence

Kyle LaFevre

David J Gulbransen

Roger Frederick DuPont

Jason Inman

Osman Musa

Kyle Lafevre

Roger Frederick Dupont

A lidar sensor includes an optical transmitter configured to generate a pulse of light. The lidar sensor also includes an optical receiver configured to receive the pulse of light generated by the optical transmitter and reflected off an object in a field of view. The optical receiver includes a photodetector configured to generate a photocurrent pulse corresponding to the received pulse of light. A receiver circuit is electrically connected to the photodetector. The receiver circuit includes a current mirror providing multiplication of the photocurrent pulse provided by the photodetector. The receiver circuit is also configured to convert the photocurrent pulse to a voltage pulse and provide the voltage pulse as an output.

Lidar sensor with high dynamic range pulse receiver

A receiver circuit for a sensor includes a photosensitive input circuit and a logarithmic-signal circuit including a PN junction coupled to a pulse voltage node. The pulse voltage node may be coupled to the P-type terminal of the PN junction and an output of the photosensitive input circuit. In some examples, the receiver circuit also may include a linear-signal circuit and/or a square-root-signal circuit.

High dynamic range receiver for a LIDAR sensor

A HDR CTIA pixel which provides automatic gain selection, and spatial and temporal coherence. The pixel comprises an input node for connection to a photocurrent, and an output node. The pixel includes a CTIA which comprises a 'high gain' integration capacitor and a first reset switch connected between the input and output nodes, a 'low gain' integration capacitor connected between the input node and a first node, a second reset switch connected between the first node and the output node, and a first FET connected across the second reset switch. In operation, the first FET is off during the reset phase, and is conditionally turned on during or after the integration phase. The CTIA also includes an amplifier having an inverting input connected to the input node and an output connected to the output node. The pixel can be operated in &#x201c;static low-gain control&#x201d; and &#x201c;dynamic low-gain control&#x201d; modes.

High dynamic range CTIA pixel

A pixel comprising a pinned photodiode (PPD) which generates a photocurrent I, a transfer gate connected in series between the PPD and a first node, a low-gain select transistor connected between the first node and a second node, a reset transistor connected between the second node and a reset voltage, a capacitance connected between the second node and a first constant potential, and a source-follower transistor whose source, gate and drain are connected to an output node, the first node and a second constant potential, respectively. When properly arranged, a vertically integrated (3D) global-shutter pinned PPD pixel is provided, which uses an overflow integration capacitor and subthreshold conduction of the reset transistor for increased dynamic range. Global shutter operation is achieved by storing the pixel output on sampling capacitors in another semiconductor layer at the end of integration.

Global-shutter vertically integrated pixel with high dynamic range

A column-parallel dual-gain single-slope ADC comprises an input for receiving a signal V, a sample-and-hold stage which receives Vand outputs sampled signal V, a comparator, a counter, and a ramp generator which generates high-gain (HG) and low-gain (LG) ramps, with the ratio of the LG ramp slope to the HG ramp slope being greater than 1. During a coarse conversion phase, Vis compared with a threshold voltage V, and a flag is set to a first or second state depending on the comparison. During a fine conversion phase, if the flag is in the first state, the HG ramp is provided to the comparator and its output toggles when the ramp voltage becomes equal to V. If the flag is in the second state, the LG ramp is provided to the comparator and its output toggles when the LG ramp voltage becomes equal to V.

Dual-gain single-slope ADC with digital CDS

Comparator circuits suitable for use in a column-parallel single-slope ADC comprise a comparator, an input voltage sampling switch connected between an input voltage Vand a first node, and a sampling capacitor connected between the first and second nodes and which stores a voltage which varies with Vwhen the sampling switch is closed. A first reset switch is connected between the second node and a reset voltage, an isolation buffer is coupled between the second node and a comparator input, and a voltage ramp switch applies a voltage ramp Vto the first node when closed. The comparator output toggles when Vexceeds V, with the isolation buffer maintaining a nearly constant capacitive load on V. A 'ramp disconnect' feature can be used to increase the circuit's input range, and a dummy capacitor can be employed to maintain a constant capacitance on V.

Comparator circuits with constant input capacitance for a column-parallel single-slope ADC

This invention pertains to a source follower circuit suitable for receiving and buffering an input voltage and providing the buffered input voltage to a sampling capacitor via a sampling switch. The source follower circuit employs a slew enhancement circuit which enables the source follower to have fast settling for both high-to-low and low-to-high transitions.

Slew-rate enhanced energy efficient source follower circuit

A capacitive trans-impedance amplifier circuit with charge injection compensation is provided. A feedback capacitor is connected between an inverting input port and an output port of an amplifier. A MOS reset switch has source and drain terminals connected between the inverting input and output ports of the amplifier, and a gate terminal controlled by a reset signal. The reset switch is open or inactive during an integration phase, and closed or active to electrically connect the inverting input port and output port of the amplifier during a reset phase. One or more compensation capacitors are provided that are not implemented as gate oxide or MOS capacitors. Each compensation capacitor has a first port connected to a compensation signal that is a static signal or a toggling compensation signal that toggles between two compensation voltage values, and a second port connected to the inverting input port of the amplifier.

Capacitive trans-impedance amplifier circuit with charge injection compensation

A shared counter circuit for a column-parallel single-slope ADC includes an n-bit counter; n low-voltage (LV) drivers connected to receive respective counter output bits and to provide a logic high or logic low output signal which tracks the received bit, the voltage difference between the logic high and logic low output signals being less than Vdd; and a plurality of sets of regenerative latches powered by a supply voltage Vdd, each of which receives an output from a respective LV driver and latches and regenerates the received output as a rail-to-rail CMOS signal upon the occurrence of a trigger event. One typical trigger event occurs when a periodic ramp voltage exceeds an input voltage provided to the ADC which may originate, for example, from the columns of a photodetector array.

Shared counter circuit with low-voltage signal output for a column-parallel single slope ADC

A comparator circuit suitable for use in a column-parallel single-slope analog-to-digital converter comprises a comparator, an input voltage sampling switch, a sampling capacitor arranged to store a voltage which varies with an input voltage when the sampling switch is closed, and a local ramp buffer arranged to buffer a global voltage ramp applied at an input. The comparator circuit is arranged such that its output toggles when the buffered global voltage ramp exceeds the stored voltage. Both DC- and AC-coupled comparator embodiments are disclosed.

Comparator circuits with local ramp buffering for a column-parallel single slope ADC

A bootstrapped class AB CMOS output circuit and method for generating a class AB output are disclosed. The bootstrapped class AB CMOS output circuit has a voltage offset circuit coupled to an NMOS transistor and a PMOS transistor. The voltage offset circuit has a capacitor bootstrapped between the NMOS transistor and the PMOS transistor to establish a voltage offset between the NMOS transistor and the PMOS transistor to effect a class AB output. The method for generating a class AB output in a semiconductor device having a capacitor coupled to the NMOS transistor and the PMOS transistor includes providing a voltage offset across the capacitor to effect a class AB output.

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Moorpark, CA, United States of America

Mihail Milkov