Infineon Technologies Ag

Mihai-Alexandru Ionescu

Razvan-Catalin Mialtu

Radu Mihaescu

Michael Asam

Christoph Schroers

Wolfgang Horn

Hubert Fischer

Ardit Tabaku

Davide Cassata

Redouane Djeghader

Louis Janinet

Michael Ruprecht

This disclosure describes a charge pump circuit comprising a plurality of switches configured to control phases of the charge pump circuit for charging a first capacitor, a second capacitor and a third capacitor. The phases may include: a first phase that charges the first capacitor to a first voltage based on an input voltage; a second phase that charges the second capacitor to a second voltage based on the first voltage and the input voltage; a third phase that charges the first capacitor to a third voltage based on the input voltage; and a fourth phase that charges the third capacitor to a fourth voltage based the second voltage, the third voltage, and the input voltage. In some examples, one or more of the capacitors are charged with duty cycles that are less than 50 percent.

Multi-stage charge pump circuit

Voltage supply circuitry includes a high-side pin and a low-side pin configured to couple to a storage element and an output pin. The voltage supply further includes a high-side switching element configured to electrically couple the positive supply pin and the low-side pin based on a high-side control signal and a low-side switching element configured to electrically couple the reference supply pin and the low-side pin based on a low-side control signal. The voltage supply further including driver circuitry configured to generate the high-side control signal and the low-side control signal for operating in a charge pump mode when the storage element is arranged in a charge pump configuration with the voltage supply circuitry and to generate the high-side control signal and the low-side control signal for operating in a boost converter mode when the storage element is arranged in a boost converter configuration with the voltage supply circuitry.

Voltage supply circuitry with charge pump mode and boost converter mode

In some examples, a device includes at least one input node configured to receive a signal indicating a current through a conductor to a load. The device also includes circuitry configured to determine a first magnitude of the received signal in a first frequency range by applying a first bandpass filter to the received signal. The circuitry is also configured to determine a second magnitude of the received signal in a second frequency range by applying a second bandpass filter to the received signal. The processing circuitry is further configured to determine that an electric arc has occurred on the conductor based on the first magnitude and the second magnitude.

Electric arc detection based on frequency analysis

An information storage circuit having a first memory portion configured to store a first validity bit and first data; a second memory portion configured to store a second validity bit and second data; and a subcircuit configured to: write the first data to the first memory portion and the second data to the second memory portion sequentially; and set the first and second validity bits to indicate which of the first data and second data is valid.

Systems and methods for storing information

Embodiments relate to multi-contact sensor devices and operating methods thereof that can reduce or eliminate offset error. In embodiments, sensor devices can comprise three or more contacts, and multiple such sensor devices can be combined. The sensor devices can comprise Hall sensor devices, such as vertical Hall devices, or other sensor types in embodiments. Operating modes can be implemented for the multi-contact sensor devices which offer significant modifications of and improvements over conventional spinning current principles, including reduced residual offset.

Embodiments relate to reliably storing information in a sensor or other device. In an embodiment, information storage circuitry comprises independent, redundant memory portions and error detection circuitry. The circuit can operate in cooperation with a memory writing procedure that utilizes a validity bit and sequentially writes to one or the other of the redundant memory portions such that at least one of the memory portions has data that is valid and can be recognized as such.

Growing community of inventors

Graefelfing, Germany

Mihai-Alexandru Ionescu