Nxp B.v.

Koninklijke Philips Corporation N.v.

St-ericsson Sa

Pxp B.v.

Mihai Adrian Tiberiu Sanduleanu

Eduard Ferdinand Stikvoort

Dominicus Martinus Wilhelmus Leenaerts

Dave Willem Van Goor

Etienn Robert Gerald Dugast

Idrissa Cissé

A detector arrangement for detecting a frequency error between an input signal (DATA) and a reference signal. The detector arrangement comprising first latch circuitry (L, L) for sampling a quadrature component (CKQ) of the reference signal based on the input signal, to generate a first binary signal (PDQ); second latch circuitry (L, L) for sampling an in-phase component (CKI) of the reference signal based on the input signal, to-generate a second binary signal (PD I); third latch circuitry (L) for sampling the first binary signal based on the second binary signal, to generate the frequency error signal (FD). The detector further comprising control circuitry (TS) for selectively suppressing operation of a charge pump () to which the first binary signal (PDQ) is supplied, in response to a control signal derived from the second binary signal.

Fast phase-frequency detector arrangement

Charge pump for providing an output current for charging and discharging a filter in accordance with an input signal, said charge pump comprising a first current source connectable with the input signal for driving the current source and adapted to providing a first current equal to a constant current Io plus a variable current &#x394;x, said variable current &#x394;x being directly proportional to the input signal, a second current source connectable with the input signal for driving the current source and adapted to providing a second current equal to the constant current Iminus said variable current &#x394;x, and an output for providing the output current, wherein said output is connected to both the first and second current source in such a way, that the output current is equal to a difference between the first and second current.

Differential charge pump with common mode control

It is disclosed a combinatorial logic circuit comprising a first logic block (B) coupled to a supply terminal (V) via a first resistor means (RI) and via a second resistor means (R) for receiving respective first and second supply currents (). The circuit further comprises a second logic block (B) coupled to the supply terminal (V) via the first resistor means (R) and via the second resistor means (R) for receiving respective third and fourth supply currents (). A first output terminal (Q&#x2212;) coupled to the first block (B) and to the first resistor means (R). A second output terminal (Q+) coupled to the second logic block (B) and to the second resistor means (R). A first current source (I) coupled to at least one of the first output terminal (Q&#x2212;) and/or second output terminal (Q+) for providing a first supply current (I) through the first resistor means (R), which is substantially equal to a second supply current (I) through the second resistor means (R).

Combinatorial logic circuit

Devices () comprising feedback-less amplifiers () that are gain controlled introduce linear relationships between output signals and input signals of the feedback-less amplifiers () by providing the feedback-less amplifiers () sub-circuits in the form of first transistors () operated in their triode regions for receiving input signals and second sub-circuits in the form of second transistors () for receiving control signals and third sub-circuits in the form of resistors () for generating output signals, whereby the respective first and second and third sub-circuits form a serial path. Second circuits () receive gain signals and convert the gain signals into the control signals. The control signals are copies of the gain signals. The second circuits () comprise current sources () and third and fourth transistors (). The current sources () comprise fifth and sixth transistors (). The second circuits () further comprise voltage sources () further current sources. Third circuits () compensate common mode currents.

Device comprising a feedback-less gain controlled amplifier

A Phase Locked Loop () used in a data and clock recovery comprising a frequency detector () including a quadricorrelator (), the quadricorrelator () comprising a frequency detector including double edge clocked bi-stable circuits () coupled to a first multiplexer () and to a second multiplexer () being controlled by a signal having a same bitrate as the incoming signal (D), and a phase detector (DFF) controlled by a first signal pair (PQ,provided by the first multiplexer () and by a second signal pair (PI,) provided by the second multiplexer ().

PLL using unbalanced quadricorrelator

The present invention provides a driving circuit () in particular for driving a laser diode () or a modulator, at data speed in the order of Gb/s. The driving circuit () has a low-voltage, high-speed output stage capable of driving efficiently a laser diode () or a modulator The driver circuit () comprises a chain of circuits, said chain comprising a slew-rate control circuit, at least one translinear amplifier (), a push/pull stage (), and an output stage () for driving the load current. Due to its versatility, the driver can be used in other applications e.g. line drivers, cable drivers, high-speed serial interfaces for back-plane interconnect, etc. The driver can work at low supply voltages, e.g. 3.3V nominal down to 2.7V, with high power efficiency. One major clue is to use entirely the large signal current produced by the output stage, e.g. in the driven laser diode, without wasting current in supply lines.

Low voltage, high-speed output-stage for laser or modulator driving

The present invention relates to a detector arrangement and a charge pump circuit for a recovery circuit recovering timing information for random data. The detector arrangement comprises a first latch circuit for sampling a quadrature component of a reference signal based on an input signal, to generate a first binary signal, a second latch circuit for sampling an in-phase component of the reference signal based on the input signal, to generate a second binary signal, and a third latch circuit for sampling the first binary signal based on the second binary signal, to generate a frequency error signal. Furthermore, the charge pump circuit comprises a differential input circuit and a control circuit for controlling a tail current of the differential input circuit in response to a frequency-locked state of frequency detector arrangement.

A latch circuit comprising, a differential input with a non-inverting input (D+) and an inverting input (D&#x2212;). The latch further comprises a differential output with a non-inverting output (Q+) and an inverting output (Q&#x2212;). One of the outputs (Q&#x2212;) is coupled to one of the inputs input (D+) having an opposite polarity. The latch further comprises a control input for receiving a control signal (V) for determining a threshold for an input signal (In) such that if the input signal is at larger than the threshold the non-inverting output is in a HIGH logic state and in a LOW state if the input signal is smaller than the threshold.

Latch circuit

A Phase Locked Loop () comprising a frequency detector () including a balanced quadricorrelator (), the loop () being characterized in that the quadricorrelator () comprises double edge clocked bi-stable circuits () coupled to multiplexers () being controlled by a signal having the same bitrate as the incoming D signal (D).

PLL with balanced quadricorrelator

A track and hold circuit () comprising:&#x2014;a linear amplifier () receiving a differential analog signal (D+, D&#x2212;) and being controlled by a first binary clock signal (H+) having a first phase,&#x2014;the linear amplifier () providing a feed-forward input signal substantially equal with the differential analog signal (D+, D&#x2212;) to a pseudo latch circuit () in the first phase of the first binary clock signal (H+), said pseudo latch circuit () being controlled by a second binary clock signal (H&#x2212;) for memorizing the input signal and providing a differential output signal (LD+, LD&#x2212;) substantially equal with the input signal during a second phase of the first binary clock signal (H&#x2212;), the second binary clock signal being substantially in antiphase with the first binary clock signal (H+).

Track and hold circuit

A tracking data cell () comprising:&#x2014;a pair of track and hold circuits (') coupled to a first multiplexer (),&#x2014;a clock signal (H+, H&#x2212;) being inputted substantially in anti-phase in the respective track and hold circuits (&#x2032;) for determining a receipt of a data signal (D+, D&#x2212;) having a rate, &#x2014;said track and hold circuits (&#x2032;) providing an output signal (O) having a substantially half rate.

Circuit for use in frequency or phase detector

Voltage controlled oscillator comprising a LC tank circuit (L, C, R) coupled to modulator means and characterized in that the modulator means are coupled to amplifier means via an adder for generating a quadrature periodical output signal having a frequency in a relative wide range, the frequency being controlled by a control signal (V.sub.T) provided to the modulator means.

Voltage controlled LC tank oscillator

The present invention concerns a phase Detector for detecting a phase difference between a data clock DATA-CLK and a reference clock REF-CLK using a data signal DATA. A trasnsition of the data signal DATA is synchronous with a transition of the data clock DATA-CLK. The data clock DATA-CLK and the reference clock REF-CLK have the same frequency. The phase detector includes first signal generator for generating a first binary signal ERRQ a second signal generator for generating a second binary signal ERRI. The pulse width of the second binary signal ERRI is equal to a second time difference &#x394;Tbetween a transition of the data signal DATA and a transition of the second reference clock signal CKI adjacent to the transition of the data signal DATA.

Phase detector

A linear amplifier circuit comprising a first differential amplifier (DA) having a differential input terminals (I+, I&#x2212;) for receiving a binary input signal, and a differential output terminals (O+,O&#x2212;), a second differential amplifier (DA) having input terminals coupled to the differential input terminals (I+, I&#x2212;). The amplifier further comprises, a third differential amplifier (DA) coupled in cascade to the second differential amplifier (DA) and having its output cross-coupled to the differential output terminals in a feedforward connection, and a capacitor (C) coupled to the third differential amplifier (DA) for determining an increase of a bandwidth of the linear amplifier, a current flowing through the capacitor (C) being proportional with a derivative of the differential input signal (I+, I&#x2212;).

Linear amplifier

The present invention relates to a charge pump, in particular for use in a tuning system including a phase-locked loop, for generating currents, including a current amplifier, wherein the current amplifier includes a translinear circuit.

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Eindhoven, Netherlands

Mihai Adrian Tiberiu Sanduleanu