Imec

Interuniversitair Microelektronica Centrum (imec)

Miguel Miranda

Francky Catthoor

Antonis Papanikolaou

Hua Wang

Bart Dierickx

Hugo De Man

Philippe Roussel

Ankur Anchlia

Stefan Janssens

Jin Guo

Martin Janssen

First several possible working points are stored with different mappings to available modules. Each of these working points involves different trade-offs for important criteria related to performance and costs. At the design stage, these trade-off points for the criteria are not calibrated to the actual run-time conditions. Subsequently, based on actual values of the leakage criteria caused by temperature variations and/or ageing at given run-time conditions for (a subset of) the working points, it is possible to calibrate the trade-off curves and use a run-time controller to select the most suited working points afterward for an actual circuit. These active working points are selected to just meet the necessary system requirements on performance, while minimizing any of the important cost parameters.

Method and apparatus for designing and manufacturing electronic circuits subject to leakage problems caused by temperature variations and/or aging

Methods and apparatus are described in which, at design-time a thorough analysis and exploration is performed to represent a multi-objective 'optimal' trade-off point or points, e.g. on Pareto curves, for the relevant cost (C) and constraint criteria. More formally, the trade-off points may e.g. be positions on a hyper-surface in an N-dimensional Pareto search space. The axes represent the relevant cost (C), quality cost (Q) and restriction (R) criteria. Each of these working points is determined by positions for the system operation (determined during the design-time mapping) for a selected set of decision knobs (e.g. the way data are organized in a memory hierarchy). The C-Q-R values are determined based on design-time models that then have to be 'average-case' values in order to avoid a too worst-case characterization. At processing time, first a run-time BIST manager performs a functional correctness test, i.e. checks all the modules based on stored self-test sequences and &#x201c;equivalence checker&#x201d; hardware. All units that fail are deactivated (so that they cannot consume any power any more) and with a flag the run-time trade-off controllers, e.g. Pareto controllers, are informed that these units are not available any more for the calibration or the mapping. At processing time, also a set of representative working points are &#x201c;triggered&#x201d; by an on-chip trade-off calibration manager, e.g. a Pareto calibration manager, that controls a set of monitors which measure the actual C-Q-R values and that calibrates the working points to their actual values. Especially timing monitors require a careful design because correctly calibrated absolute time scales have to be monitored.

Method and apparatus for designing and manufacturing electronic circuits subject to process variations

A method for determining an estimate of statistical properties of an electronic system comprising individual components subject to manufacturing process variability is disclosed. In one aspect, the method comprises obtaining statistical properties of the performance of individual components of the electronic system, obtaining information about execution of an application on the system, simulating execution of the application based on the obtained information about execution of the application on the system for a simulated electronic system realization constructed by selecting individual components with the obtained statistical properties determining the delay and energy of the electronic system, and determining the statistical properties of the delay and energy of the electronic system.

Methods for characterization of electronic circuits under process variability effects

One inventive aspect relates to a method of determining an estimate of system-level yield loss for an electronic system comprising individual components subject to manufacturing process variability leading to manufacturing defects. The method comprises obtaining a description of the composition of the electronic system in terms of which individual components are used. The method further comprises obtaining statistical properties of the performance of individual components of the electronic system with respect to first and second performance variables, e.g. energy consumption and delay, the statistical properties including correlation information of the first and second performance variables. The method further comprises obtaining information about execution of an application on the system, e.g. a number of accesses of a component by an application. The method further comprises propagating the statistical properties of the first and second performance variables of the individual components to the electronic system so that the correlations between the first and second performance variables are preserved, the propagating taking into account the application information.

Method for exploring feasibility of an electronic system design

A method of determining the behavior of an electronic system comprising electronic components under variability is disclosed. In one aspect, the method comprises for at least one parameter of at least one of the electronic components, showing variability defining a range and a population of possible values within the range, each possible value having a probability of occurrence, thereby defining an input domain. The method further comprises selecting inputs randomly from the input domain, wherein the probability to sample (PTS) is obtained from the probability of occurrence (PTOIR). The method further comprises performing simulation to obtain the performance parameters of the electronic system, thereby defining an output domain sample. The method further comprises aggregating results of the individual computations into the parameter/variability of the electronic system and assigning a frequency of occurrence (FoO) to the resulting sample, the parameter variability and the frequency of occurrence defining the behavior.

Simulation method for efficient characterization of electronic systems under variability effects

One aspect of the invention includes a method of address expression optimization of source-level code. The source-level code describes the functionality of an application to be executed on a digital device. The method comprises first inputting first source-level code that describes the functionality of the application into optimization system. The optimization system then transforms the first source-level into a second source level that has fewer nonlinear operations than the first source-level code.

System and method for optimizing source code

The present invention provides a driver circuit for driving a line terminated by a load, wherein said driver circuit is configurable for design time selected energy/delay working points. The configuration capability is used, e.g. during run-time, for dynamically selecting a suitable energy/delay working point, given the circumstances wherein said driver circuit has to operate. The driver circuit is in particular targeted for on-chip communication, but is not limited thereto.

Power-aware configurable driver circuits for lines terminated by a load

An aspect of the present invention provides a design environment in which a floorplan of a semiconductor device is optimised by taking into account activation or access frequency information to and from resources. Since segmented bus architecture is also a good alternative approach for the power consumption of the network, the floorplanning approach for energy optimization of the communicating network is adapted for such architectures in embodiments of the present invention. The provided method comprises both architecture optimizations as well as physical design optimizations.

Resource activity aware system for determining a resource interconnection pattern within an essentially digital device and devices created therewith

A programmable processing engine and a method of operating the same is described, the processing engine including a customized processor, a flexible processor and a data store commonly sharable between the two processors. The customized processor normally executes a sequence of a plurality of pre-customized routines, usually for which it has been optimized. To provide some flexibility for design changes and optimizations, a controller for monitoring the customized processor during execution of routines is provided to select one of a set of pre-customized processing interruption points and for switching context from the customized processor to the flexible processor at the interruption point. The customized processor can then be switched off and the flexible processor carries out a modified routine. By using sharable a data store, the context switch can be chosen at a time when all relevant data is in the sharable data store. This means that the flexible processor can pick up the modified processing cleanly. After the modified processing the flexible processor writes back new data into the data store and the customized processor can continue processing either where it left off or may skip a certain number of cycles as instructed by the flexible processor, before beginning processing of the new data.

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Kessel-lo, Belgium

Miguel Miranda