International Business Machines Corporation

Amkor Technology, Inc.

Other

Miguel Angel Jimarez

Lisa Jeanine Jimarez

Voya Rista Markovich

Cynthia Susan Milkovich

Robert Francis Darveaux

Ju Hoon Yoon

Ki Wook Lee

Ross William Keesler

Jae Dong Kim

Marybeth Perrino

Michael Barrow

Dae Keun Park

Mark Vincent Pierson

Kenneth Michael Fallon

John M Lauffer

William E Wilson

Roy H Magnuson

John A Welsh

Jim P Paoletti

Irv Memis

Joseph Edward Zdimal

Charles Hampton Perry

Brenda Lee Peterson

Charles Felix Gabriel

Charles Gerard Woychik

Lawrence H White

Sanjeev Balwant Sathe

Li Li

Son K Tran

Amit Kumar Sarkhel

Krishna Darbha

Donald I Mead

Rajinder S Rai

Thomas M Culnane

Cheryl L Tytran-Palomaki

Matthew M Reiss

Tien Y Wu

David N Cokely

Ahmer Raza Syed

Reinaldo Anthony Neira

Jeff Watson

A novel die seal design, and method for utilization thereof, controls contact of a mold material with the surfaces of a semiconductor die during application, reducing stresses due to a mismatch of the coefficient of thermal expansion of the mold material and the semiconductor die, thereby reducing cracking of the semiconductor die, resulting in increased yields and lower costs, and permits reuse of elements of a mold tool over a range of die sizes.

Method for controlling molding compound geometry around a semiconductor die

An exposed die overmolded flip chip package includes a substrate. A die is flip chip mounted to an upper surface of the substrate. The package further includes a mold cap filling a space between an active surface of the die and the upper surface of the substrate. The mold cap includes a principal surface, sidewalls extending from the upper surface of the substrate to the principal surface, an annular surface coplanar with the inactive surface of the die and extending outward from a peripheral edge of the inactive surface of the die, and protruding surfaces extending between the principal surface and the annular surface. The mold cap does not cover the inactive surface of the die such that heat transfer from the die to the ambient environment is maximized and the package thickness is minimized.

Exposed die overmolded flip chip package and fabrication method

An exposed die overmolded flip chip package includes a substrate. A die is flip chip mounted to an upper surface of the substrate. The package further includes a mold cap filling a apace between an active surface of the die and the upper surface of the substrate. The mold cap includes a principal surface, sidewalls extending from the upper surface of the substrate to the principal surfaces, an annular surface coplanar with the inactive surface of the die and extending outward from a peripheral edge of the inactive surface of the die, and protruding surfaces extending between the principal surface and the annular surface. The mold cap does not cover the inactive surface of the die such that heat transfer from the die to the ambient environment is maximized and the package thickness is minimized.

Exposed die overmolded flip chip package

Exposed die overmolded flip chip package method

A method of forming a printed circuit card with a metal power plane layer between two photoimageable dielectric layers is provided. Photoformed metal filled vias and plated through holes are in the photopatternable material, and signal circuitry is on the surfaces of each of the dielectric materials connected to the vias and plated through holes. A border may be around the card including a metal layer terminating in from the edge of one of the dielectric layers. Copper foil with clearance holes is provided. First and second layers of photoimageable curable dielectric material are on opposite sides of the copper. Patterns are developed on the first and second layers of the photoimageable material to reveal the metal layer through vias. Through holes are developed where holes were patterned in both dielectric layers. The surfaces of the photoimageable material, vias and through holes are metallized by copper plating, preferably using photoresist.

Method of forming printed circuit card

A method for forming a plated microvia interconnect. An external dielectric layer (EDL) is mounted on a surface of the substrate and is in direct mechanical contact with a conductive element included in the surface. An opening formed in the EDL exposes the conductive element and creates a microvia in the EDL. A sidewall and bottom wall surface of the microvia is treated to promote copper adhesion to the sidewall and bottom wall surfaces. The sidewall and bottom wall surfaces are plated to form a layer of copper thereon. The layer of copper is in direct mechanical and electrical contact with the conductive element. A wet solder paste deposited on the layer of copper overfills a remaining portion of the microvia. The solder paste is reflowed to form a solder bump in and over the remaining portion of the microvia to form the plated microvia interconnect.

Method for forming a plated microvia interconnect

An electronic package and method of making the electronic package is provided. A layer of dielectric material is positioned on a first surface of a substrate which includes a plurality of conductive contacts. At least one through hole is formed in the layer of dielectric material in alignment with at least one of the plurality of conductive contacts. A conductive material is positioned in the at least one through hole substantially filling the through hole. At least one conductive member is positioned on the conductive material in the through hole and in electrical contact with the conductive material. The electronic package improves field operating life of an assembly which includes a semiconductor chip attached to a second surface of the substrate and a printed wiring board attached to the conductive members.

Method of making an electronic package

A method of using x-rays to align screen printing of flip chip using x-ray sub-assembly in a chip fabricating assembly. X-rays are directed onto a substrate having receptor pads and a printing screen having fine apertures. The substrate is aligned with the printing screen based on the detection and analysis of the real-time image generated from the x-rays passing through the substrate and printing screen. The x-ray alignment system is capable of aligning gold plated receptor pads of five microns or less and disposed upon a low light contrast ceramic (e.g., 9011 alumina) substrate with a screen printing stencil having very small apertures of less than 125 microns.

X-ray alignment system for fabricating electronic chips

A method and structure to electrically couple a semiconductor device to a substrate that is divided into a plurality of segments. Alternatively, a semiconductor device may be divided into a plurality of segments and the plurality of segments are electrically coupled to a single substrate.

Stress reduction in flip-chip PBGA packaging by utilizing segmented chips and/or chip carriers

A method of forming a printed circuit card with a metal power plane layer between two photoimageable dielectric layers is provided. Photoformed metal filled vias plated through holes are in the photopatternable material, and signal circuitry is on the surfaces of each of the dielectric materials connected to the vias and plated through holes. A border may be around the card including a metal layer termination in from the edge of one of the dielectric layers. Copper foil with clearance holes is provided. First and second layers of photoimageable curable dielectric material are on opposite sides of the copper. Patterns are developed on the first and second layers of the photoimageable material to reveal the metal layer through vias. Through holes are developed where holes were patterned in both dielectric layers. The surfaces of the photoimageable material, vias and through holes are metallized by copper plating, preferably using photoresist.

An electrical structure, and associated method of fabrication, for reducing thermally induced strain in a structure that couples a first conductive body of a first substrate to a second conductive body of a second substrate (e.g., a chip to a chip carrier; a chip carrier to a circuit card). The melting point of the first conductive body exceeds the melting point of the second conductive body. The second conductive body may include eutectic lead-tin alloy, while the first conductive body may include non-eutectic lead-tin alloy. A portion of the first conductive body is coated with, or volumetrically surrounded by, a material that is nonsolderable and nonconductive. The first and second conductive bodies are coupled mechanically and electrically by surface adhesion at an uncoated portion of the first conductive body, by application of a temperature that lies between the melting points of the first and second conductive bodies.

Flip chip C4 extension structure and process

Growing community of inventors

Newark Valley, NY, United States of America

Miguel Angel Jimarez