Meta Platforms, Inc.

Meta Platforms Technologies, LLC

Miguel Angel Guerrero

Liangzhen Lai

Simon James Hollis

Drew Eric Wingard

Jun Wang

Harshit Khaitan

Neeraj Upasani

Wojciech Stefan Powiertowski

Gregory Ehmann

Xu Chen

Kyong Ho Lee

Marco Brambilla

Minli Lin

Varun Agarwal

In one embodiment, a method for accessing an instruction that is to be executed by a control agent within a computing system may include decompressing the instruction by replacing each of one or more zero-symbol run-length fields in the instruction with as many continuous zero symbols as its corresponding value and removing one or more non-zero-symbol run-length fields from the instruction. The method may also include determining that the instruction is spatial-delta-encoded based on a compression data header associated with the instruction, performing spatial-delta decoding on the instruction in response to the determination by orderly determining a spatial-delta-decoded value of each bit in the instruction, and causing the instruction to be sent to the control agent.

Compressing instructions for machine-learning accelerators

A system including a machine-learning accelerator (MLA) hardware comprising computation-control units that each have a programmable dependency matrix; and a compiler computing module configured to generate, based on a machine-learning model, dependency instructions indicating dependencies between the computation-control units; wherein the computation-control units include at least: a first computation-control unit configured to generate, after completion of a first operation, a synchronization token representing the completion of the first operation, the synchronization token specifying a recipient identifier for an intended recipient computation-control unit of the synchronization token; a second computation-control unit configured to: configure the programmable dependency matrix of the second computation-control unit according to the dependency instructions to include dependency conditions for performing operations; receive the synchronization token based on the recipient identifier; update a dependency state to reflect the received synchronization token; and execute an operation in response to a determination that the dependency state satisfies the dependency condition.

Distributed synchronization scheme

A system including a machine learning accelerator (MLA) hardware configured to perform machine-learning operations according to native instructions; an interpreter computing module configured to: generate, based on virtual instructions, machine language instructions configured to be processed by a processing hardware implementing the interpreter computing module; and cause the processing hardware to perform machine-learning operations according to the machine language instructions; and a compiler computing module associated with the MLA hardware, the compiler computing module configured to: receive instructions for performing an inference using a machine-learning model; based on the received instructions: generate the native instructions configured to be processed by the MLA hardware, the native instructions specifying first machine-learning operations associated with performing the inference; and generate the virtual instructions configured to be processed by the interpreter computing module, the virtual instructions specifying second machine-learning operations associated with performing the inference.

Architecture for virtual instructions

The disclosure describes techniques for interrupt and inter-processor communication (IPC) mechanisms that are shared among computer processors. For example, an artificial reality system includes a plurality of processors; an inter-processor communication (IPC) unit comprising a register, wherein the IPC unit is configured to: receive a memory access request from a first processor of the processors, wherein the memory access request includes information indicative of a hardware identifier (HWID) associated with the first processor; determine whether the HWID associated with the first processor matches an HWID for the register of the IPC unit; and permit, based on determining that the HWID associated with the first processor matches the HWID for the register of the IPC unit, the memory access request to indicate a communication from the first processor to at least one other processor.

Artificial reality system with inter-processor communication (IPC)

Growing community of inventors

Palo Alto, CA, United States of America

Miguel Angel Guerrero