Vlsi Technology, Inc.

Miguel A Delgado

Edward R Vokoun, Iii

Brian D Richardson

Elizabeth A Chambers

Rajive Dhar

Gregory N Carter

Ivan Sanchez

Stacy W Hall

Yu-Pin Han

John L Cain

Ying-Tsong Loh

Ramiro Solis

Stephen Cannizzaro

The invention relates generally to integrated circuits and, in particular, to methods of forming anti-fuse structures during integrated circuit manufacture. In an exemplary embodiment of the invention, a conductive base layer is formed over a semiconductor substrate. An insulating layer is formed on the conductive base layer and is patterned to expose a portion of the conductive base layer. An anti-fuse layer is formed on the insulating layer and the exposed portion of the conductive base layer. A conductive protection layer is formed on the anti-fuse layer. An anti-fuse island is formed by sequentially removing a portion of the conductive protection layer, and underlying portions of the anti-fuse layer and the insulating layer. The conductive base layer is patterned after forming the anti-fuse island. The invention provides a simplified method for the formation of anti-fuse structures which is compatible with submicron device geometries.

Method of forming anti-fuse structure

A method for forming a scribe line on a semiconductor wafer including the steps of: (a) providing a semiconductor substrate; and (b) sequentially providing a plurality of layers over the semiconductor substrate of alternating conductive and insulating types, where each of the layers is provided with an elongated opening is formed relative to a desired scribe line position, and where the openings of at least some of the plurality of layers are wider than openings of preceding layers such that at least one sidewall of a completed scribe line has a pronounced slope extending outwardly from its base. The structure of the present invention is, therefore, a scribe line having sloped sidewalls that greatly reduces scribe line contamination problems and enhances planarization during subsequent spin-on-material processes. The scribe lines can either be elongated openings in the layers, or an elongated mesa formed in the layers.

Integrated circuit scribe line structures and methods for making same

An integrated circuit having a semiconductor substrate and an anti-fuse structure formed on the semiconductor substrate. The anti-fuse structure includes a metal-one layer and an anti-fuse layer disposed above the metal-one layer. The anti-fuse layer has a first resistance value when the anti-fuse structure is unprogrammed and a second resistance value lower than the first resistance value when the anti-fuse structure is programmed. There is further provided an etch stop layer disposed above the anti-fuse layer, and an inter-metal oxide layer disposed above the etch stop layer with the inter-metal oxide layer has a via formed therein. Additionally, there is further provided a metal-two layer disposed above the inter-metal oxide layer. In this structure, a portion of the metal-two layer is in electrical contact with the anti-fuse layer through the via in the inter-metal oxide layer.

Methods and apparatus for fabricationg anti-fuse devices

A system for evacuating a reactor chamber includes a main evacuation line connected at one end thereof to the reactor chamber and at another end thereof to a means for creating a partial vacuum. A valve in the main evacuation line divides the line into a chamber side and a vacuum side. A second line is connected at one end to the vacuum side of the main evacuation line and at another end to a fluid supply source. As the valve in the main evacuation line is opened, fluid is supplied through the second line to the main evacuation line to prevent rapid, turbulence-inducing pressure drops in the reactor chamber.

Pumping system for evacuating reactor chambers

An improved method for forming vias in an anti-fuse semiconductor device through an oxide layer to an underlying metallic layer. A wet etch is performed on the oxide layer at selected regions where vias are to be formed. The wet etch is controlled such that a first recessed area is formed in the oxide layer at the selected regions. The first recessed area formed by the wet etch extends only partially through the oxide layer towards the underlying metallic layer. Additionally, the first recessed area is formed having a smoothly shaped contour. Next, a dry etch is performed on the oxide layer at the selected regions where the vias are to be formed. The dry etch is performed within the first recessed area. The second recessed area has a smaller cross sectional area than the first recessed area such that the second recessed area is peripherally bordered by the first recessed area. The second recessed area extends from the bottom of the first recessed area completely through the remaining oxide layer to the underlying metallic layer. In so doing, when amorphous silicon is deposited into the vias, cusping of the amorphous silicon within the vias is substantially reduced. As a result, the step of depositing a spacer oxide to fill in notches created by cusping of the amorphous silicon layer is eliminated. Consequently, when the amorphous silicon is removed or etched from selected strap vias, because no spacer oxide has been deposited, no deleterious residue or 'dog ears' of amorphous silicon remain within the strap vias.

Wet/dry anti-fuse via etch

A method for removing excess spacer material in the link vias and open areas of an anti-fuse structure without thinning the anti-fuse layer in the vias by overetching. In an anti-fuse structure, a spacer layer is deposited on an anti-fuse layer where vias in the structure cause a thinner layer of spacer material to be deposited in the vias. A first etch of the spacer layer is accomplished to provide protective spacers in the vias. The etch completely removes the thinner section of the spacer material between the spacers in the vias without overetch, while some spacer material portions remain on the other, open areas of the anti-fuse structure. Designated fuse vias are masked and a second etch of the leftover spacer material is accomplished. This method removes excess spacer material from link vias and other areas around the fuse vias and prevents the anti-fuse layer in the fuse vias from thinning from overetching procedures.

Growing community of inventors

San Antonio, TX, United States of America

Miguel A Delgado