Nec Corporation

Nec Electronics Corporation

Mieko Suzuki

Tetsuya Homma

Yasuaki Tsuchiya

Akira Kubo

Hiroki Koga

Takaho Tanigawa

Yukinobu Murao

There is provided an apparatus for polishing a substrate, including (a) a polishing pad formed with a plurality of through-holes through which polishing material is supplied to a surface of the polishing pad, (b) a level block on which the polishing pad is mounted, and (c) a rotatable carrier for supporting a substrate thereon, the carrier being positioned in facing relation with the level block, the level block being rotatable around a rotation axis thereof with the rotation axis being moved along an arcuate path, and causing the polishing pad to make contact with the substrate for polishing the substrate, the polishing pad having a first ring-shaped region concentric thereto where no through-holes are formed. For instance, the first ring-shaped region has a width greater than 10%, but smaller than 95% of a radius of the polishing pad. The apparatus enhances uniformity in polishing a substrate.

Chemical mechanical polishing apparatus and method of chemical mechanical polishing

A semiconductor device in which an interconnection material is buried in a hole formed in an interlevel insulating film arranged on a semiconductor substrate includes a protective layer formed on the surface of the interlevel insulating film that has a lower polishing rate than that of the interconnection material in chemical mechanical polishing. A method of manufacturing this semiconductor device is also disclosed.

Method of forming polish stop by plasma treatment for interconnection

A method and an apparatus for polishing a metal film formed on a semiconductor device are disclosed. A semiconductor wafer is immersed in an oxidizing solution before it is polished. As a result, the undesirable part of a W film deposited on the circumferential edge of the wafer is removed by etching.

Method and apparatus for polishing a metal film

The present invention provides a chemical mechanical polishing method for polishing a soft metal by supplying a polishing surface of the soft metal with a novel polishing slurry which includes at least both alumina particles as polishing particles and hydrogen peroxide as oxidizing agent, wherein the content of the alumina particles is in the range of 2-10% by weight of the total amount of the polishing slurry.

Chemical mechanical polishing method for highly accurate in-plane uniformity in polishing rate over position

A wafer polishing apparatus includes a carrier and a table. A wafer is mounted on the carrier, and the carrier includes a circumference ring provided around of the wafer. The height of the innermost portion of the circumference ring is equal to or higher than that of a surface of the wafer. The table includes a polishing pad. The carrier and the table are relatively rotated such that the wafer surface is polished by the polishing pad.

Method and apparatus polishing wafer for extended effective area of wafer

A fabrication method of a semiconductor device is provided, which enables the formation of a conductive plug in an opening of an interlevel dielectric layer without arising any void. After a first wiring layer is formed on a first interlevel electric layer, a second interlevel dielectric layer is formed on the first interlevel dielectric layer to cover the first wiring layer. A first opening is formed in the second interlevel dielectric layer. A first conductive layer is formed on or over the second interlevel dielectric layer to cover the first opening. A first protection layer is formed on the first conductive layer to cover a first depressed part of the first conductive layer. The first protection layer having a first buried part on the first depressed part. The first protection layer and the first conductive layer are polished by a CMP process until the second interlevel dielectric layer is exposed, thereby selectively leaving the first depressed part within the first opening. The first depressed part left within the first opening constitutes a first conductor plug for electrically interconnecting the first wiring layer with a second wiring layer formed to be contacted with the fist conductor plug.

Fabrication method of semiconductor device

A semiconductor device is formed with an interlayer insulation layer having its high flatness. A metal wiring is formed on a silicon substrate via a silicon oxide layer. A multi-layer silicon oxide layer that is to be the interlayer insulation film is formed over the insulation layer and the metal wiring. The multi-layer silicon layer consists of an upper most first silicon oxide layer, a lower most third silicon oxide layer and an intermediate second silicon oxide layer. The second silicon oxide layer has higher polishing rate than the first and third silicon oxide layer. By performing chemical mechanical polishing for the multilayer silicon oxide layer, a step formed by the presence of the metal layer can be satisfactorily eliminated fox planarizing the surface of the interlayer insulation film.

Fabrication process of semiconductor device

The invention provides a fabrication method of multilevel interconnections for semiconductor integrated circuits. Aluminium wiring lines are formed on a first silicon oxide film overlying a silicon substrate. A second silicon oxide film is grown by a plasma chemical vapor deposition on the wiring lines and the first silicon oxide film for a specific surface treatment of either an etching with use of fluorine compounds or an ion-implantation of fluorine compounds. A third silicon oxide film is grown on the second silicon oxide film by an atmospheric pressure chemical vapor deposition with use of organic silicon compounds and an oxygen including ozone.

Method of fabricating multilevel interconnections in a semiconductor

A method which can markedly improve the flatness of a semiconductor integrated circuit device by forming selectively a layer insulating film on an underlying substrate having level differences is disclosed. First, a Ti--W alloy film is formed on a member which brings about level differences due to wirings or the like, then a PECVD silicon oxide film is formed followed by a plasma treatment using CF.sub.4 gas. Further, a silicon oxide film is deposited by atmospheric pressure CVD using ozone and tetraethoxysilane. Then, the surface is flattened by etchback using an organic SOG film, and a silicon oxide film is formed by plasma excited CVD.

Method of producing semiconductor integrated circuit device having

A method of manufacturing a semiconductor device, incorporates the steps of: performing reactive ion etching using a fluorine compound gas to surface-treat the lower level wirings which permits selective deposition of the second silicon oxide film; selectively depositing a second silicon oxide film between said lower level wirings by a CVD method using an organic silicon compound gas and an oxidizable gas as source gases; depositing a third silicon oxide film on an entire surface and forming through holes connected to the lower wirings; and forming upper level wirings connected to the lower level wirings. Further, an additional silicon oxide film can be deposited on the major surface so as to form a side wall thereof on the lower level wirings. The reactive ion etching is then performed.

Forming multi-layered interconnections with fluorine compound treatment

A process for manufactoring a semiconductor device having a double- or multi-level interconnection structure is disclosed. The process includes steps of: forming a first level metal interconnect; then forming a first silicon oxide layer by PECVD, and forming a second silicon oxide layer by atmospheric CVD using tetraethoxysilane and oxygen containing ozone under a condition of excess ozone in which the ratio of flow-rate of ozone to flow-rate of tetraethoxysilane is about 20:1. An organic compound coating layer is formed by spin-coating accompanied by a thermal treatment. The organic compound coating layer and the second silicon oxide layer are etched-back to remove the compound oxide layer completely. A third silicon oxide layer is formed by PECVD; and forming a second level metal interconnect. A good planarization can be obtained and a failure, such as delamination or blister due to bumping, of the third silicon oxide layer can be avoided. Hence, a high yield and a high reliability of the semiconductor device having a double- or multi-level interconnection structure can be achieved.

Growing community of inventors

Tokyo, Japan

Mieko Suzuki