Hitachi Displays, Ltd.

Hitachi, Ltd.

Panasonic Liquid Crystal Display Co., Ltd.

Hitachi Chemical Company, Ltd.

Tokyo Institute of Technology

Japan Display Inc.

Mieko Matsumura

Yoshiaki Toyota

Mutsuko Hatano

Takeshi Sato

Masatoshi Wakagi

Hirotaka Hamamura

Keiji Watanabe

Isao Suzumura

Takashi Hattori

Etsuko Nishimura

Kenichi Onisawa

Yuki Mori

Naoki Tega

Keisuke Kobayashi

Toshio Miyazawa

Digh Hisamoto

Toshiyuki Mine

Mitsuhide Miyamoto

Takuo Kaitoh

Hiroshi Miki

Junichi Hanna

Yasushi Kurata

Masato Yoshida

Ryuta Tsuchiya

Junichi Sakano

Tetsufumi Kawamura

Takeshi Nojiri

Masatoshi Morishita

Haruka Shimizu

Toshiyuki Ohno

Tooru Tanaka

Shuichiro Adachi

Akihiro Orita

Akiko Kagatsume

Tsuyoshi Hayasaka

To solve a problem of realizing a large current and highly reliable power semiconductor device while shrinking a unit cell. A semiconductor device according to the present invention includes a plurality of p-type body regions extending in a first direction. The semiconductor device further includes: a JFET region formed to extend in the first direction between p-type body regions which are adjacent to each other in a second direction orthogonal to the first direction; an n-type source region formed to extend in the first direction within a p-type body region and separate from an end side surface of the p-type body; and a channel region formed to extend in the first direction and in a top layer portion of a p-type body region between an end side surface of the p-type body region and an end side surface of an n-type source region.

Semiconductor device and power conversion device

A MOSFET using a SiC substrate has a problem that a carbon-excess layer is formed on a surface by the application of mechanical stress due to thermal oxidation and the carbon-excess layer degrades mobility of channel carriers. In the invention, (1) a layer containing carbon-carbon bonds is removed; (2) a gate insulating film is formed by a deposition method; and (3) an interface between a crystal surface and the insulating film is subjected to an interface treatment at a low temperature for a short time. Due to this, the carbon-excess layer causing characteristic degradation is effectively eliminated, and at the same time, dangling bonds can be effectively eliminated by subjecting an oxide film and an oxynitride film to an interface treatment.

Silicon carbide semiconductor device and method for manufacturing same

A composition for forming a passivation layer, comprising a compound represented by Formula (I): M(OR). In Formula (I), M comprises at least one metal element selected from the group consisting of Nb, Ta, V, Y and Hf, each Rindependently represents an alkyl group having from 1 to 8 carbon atoms or an aryl group having from 6 to 14 carbon atoms, and m represents an integer from 1 to 5.

Composition for forming passivation layer, semiconductor substrate having passivation layer, method of producing semiconductor substrate having passivation layer, photovoltaic cell element, method of producing photovoltaic cell element and photovoltaic cell

Provided is a technique of securing reliability of a gate insulating film, as much as in a Si power MOSFET, in a semiconductor device in which a semiconductor material having a larger band gap than silicon is used, and which is typified by, for example, an SiC power MOSFET. In order to achieve this object, in the in the SiC power MOSFET, the gate electrode GE is formed in contact with the gate insulating film GOX, and is formed of the polycrystalline silicon film PFhaving the thickness equal to or smaller than 200 nm, and the polycrystalline silicon film PFformed in contact with the polycrystalline silicon film PFand having any thickness.

Semiconductor device and method of manufacturing the same

A solar cell including a substrate, a nanopillarhaving diameter Dconnected to the substrate, and a nanopillarhaving diameter Dconnected to the substrateis characterized in that Dis greater than Din order to realize a solar cell having, as the surface structure, a nanopillar array structure with which it is possible to prevent reflection within the broad wavelength region of solar light. A nanopillar array structureformed from two types of nanopillars having different diameters has a point of minimum reflectivity of a nanopillar array structure formed from the nanopillarhaving diameter Dand a point of minimum reflectivity of a nanopillar array structure formed from the nanopillarhaving diameter Dand therefore, is capable of preventing reflection within the broad wavelength region of solar light.

Solar cell

An image display unit is provided for which it is possible to reduce the number of ion plantation and photolithographic processes required to manufacture the device. A gate electrode GT is a laminated structure of a thin bottom layer metal film GMB and a top layer metal film GMT. A top electrode of a storage capacitor Cst is formed of the bottom layer metal film GMB and ion implantation for the top electrode is performed at the same time as the ion implantation of source-drain electrodes. The gate electrode of a PMOSTFT of the device is also formed with the bottom layer metal GMB, and the ion implantation for threshold adjustment is performed by using the same resist.

Image display unit

A display device includes a plurality of thin-film transistors formed on a substrate on which a display area is formed. The display device also includes a gate electrode, a gate insulating film formed so as to cover the gate electrode, an semiconductor layer in an island shape formed on an upper surface of the gate insulating film so as to superimpose the gate electrode without protruding from the gate electrode when viewed planarly, an insulating film formed so as to cover the semiconductor layer, and a pair of electrodes electrically connected to the semiconductor layer respectively through a pair of through holes that are formed at the insulating film. The semiconductor layer is formed by sequentially laminating a crystalline semiconductor layer and an amorphous semiconductor layer. The pair of electrodes is respectively formed by sequentially laminating a semiconductor layer doped with impurities and a metal layer.

Display device

A bottom gate-type thin film transistor includes a gate insulating film, an interlayer insulating film formed on the gate insulating film, having an opening which is formed in a formation region of a gate electrode, and a semiconductor film formed on the interlayer insulating film so as to cover the opening. The interlayer insulating film contains nitrides in an amount larger than that in the gate insulating film, and the semiconductor film includes a microcrystalline semiconductor film or a polycrystalline semiconductor film formed on semiconductor crystalline nuclei which are formed on the gate insulating film and the interlayer insulating film and contain at least Ge.

Thin film transistor and manufacturing method thereof

Provided is a method of promoting a deposition of semiconductor crystal nuclei on an insulating film such as a silicon oxide film even at a low temperature of 450&#xb0; C. or lower in a reactive thermal CVD method. As one means thereof, a first semiconductor film is formed on an insulating substrate, and then semiconductor crystal nuclei are formed on parts of the first semiconductor film and simultaneously the first semiconductor film other than that in forming regions of the semiconductor crystal nuclei and their peripheries is removed by etching. Thereafter, a second semiconductor film is formed with using the semiconductor crystal nuclei as seeds.

Semiconductor device, manufacturing method thereof, and display apparatus using the semiconductor device

A display device includes a plurality of thin-film transistors formed on a substrate on which a display area is formed. At least one of the plurality of thin-film transistors includes a gate electrode, agate insulating film formed to cover the gate electrode, an interlayer insulating film formed on an upper surface of the gate insulating film and having an opening formed in an area where the gate electrode is formed in plan view, a pair of heavily-doped semiconductor films arranged on an upper surface of the interlayer insulating film with the opening interposed therebetween, a polycrystalline semiconductor film formed across the opening and formed in the area, the polycrystalline semiconductor film being electrically connected to the pair of heavily-doped semiconductor films, and a pair of electrodes formed to overlap the pair of heavily-doped semiconductor films, respectively, without overlapping the polycrystalline semiconductor film.

The display device having a thin film transistor formed on a substrate including a display portion is provided. The thin film transistor including: a gate electrode; a gate insulating film formed so as to cover the gate electrode; a semiconductor laminated film formed on top the gate insulating film so as to extend over the gate electrode, the semiconductor laminated film being formed by laminating at least a polycrystalline semiconductor film and an amorphous semiconductor film, a first electrode and a second electrode disposed on top of the semiconductor laminated film so as to be opposed to each other across a region superposing the gate electrode. In the display device, the semiconductor laminated film is formed immediately below a wiring extending from the first electrode and immediately below a wiring extending from the second electrode.

Display device and method of manufacturing the same

A liquid crystal display, having an improved application of electric field to the molecules of liquid crystal, includes a substrate and a pixel array bonded to the surface of this substrate, and the pixel array includes at least a thin-film transistor and a pixel electrode connected with this thin-film transistor, and the pixel electrode is formed in a layer higher than the thin-film transistor in relation to the substrate.

Liquid crystal display

Each TFT for driving each of a plurality of pixels arranged in a matrix-like configuration is configured using a stagger-type polycrystalline-Si TFT. A gate electrode, which is composed of a high-heat-resistant material capable of resisting high temperature at the time of polycrystalline-Si film formation, is disposed at a lower layer as compared with the polycrystalline-Si layer that forms a channel of each TFT. A gate line, which is composed of a low-resistance material, is disposed at an upper layer as compared with the polycrystalline-Si layer. The gate electrode and the gate line are connected to each other via a through-hole bored in a gate insulation film. Respective configuration components of each organic electro-luminescent element are partially co-used at the time of the line formation, thereby suppressing an increase in the steps, processes, and configuration components.

Organic electro-luminescent display apparatus

Three layers are formed on a TFT substrate SUB. The three layers include a first transparent electrode PSL, a second transparent electrode CSLand a third transparent electrode PSL, all of which are laminated in parallel to the substrate surface. Two auxiliary capacitances to a liquid crystal capacitance are formed between the first transparent electrode PSLand the second transparent electrode CSLand between the second transparent electrode CSLand the third transparent electrode PSL

Liquid crystal display device

In either of a source side and a drain side of an insular semiconductor thin film, a gate electrode is extended without a break along the contour of the insular semiconductor thin film to provide a branch closed circuit, thereby removing a current component path to server as a sub-channel in the edge of the insular semiconductor thin film, in order to eliminate current components due to the concentration of a gate electric field in silicon thin-film edges occurring in edges of an insular semiconductor thin film of top gate type thin-film transistors and a shift of threshold due to fixed charges in the periphery of the silicon thin-file edges.

Growing community of inventors

Kokubunji, Japan

Mieko Matsumura