Fujitsu Corporation

Mie Tonosaki

Tomoyuki Okawa

Hitoshi Sakurai

Masaki Ukai

A cache memory built in a processor comprising a plurality of independent memory blocks, pass/fail information memory unit memorizing a presence/absence of a failure occurring in each of the memory blocks, and a screening control function substituting a sound memory block for a failed memory block based on a memory content in the pass/fail information memory unit.

Cache memory, processor, and production methods for cache memory and processor

A cacheable memory access space receives memory access addresses having different data structures according to a status of a cache capacity from a processor. A cache hit detector determines whether data has been hit based on a mode signal, an enbblk [n] signal, and a signal indicating whether the way is valid or invalid, which are preset in the cache hit detector, a tag comparison address received from the cacheable memory access space, and a tag received from the storage unit.

Cache memory and method of controlling memory

A circuit for driving and controlling a second cache that is incorporated in a processor and comprises a plurality of RAM. The circuit comprises a second-cache control unitA and a chip-enable control unit. The second-cache control unitA receives an access request for an access to the second cache and designates some of the RAMs, which need not operate, in accordance with the type or address of the access request, or both. The chip-enable control unitoutputs an intra-macro stop-instructing signal to the RAMs that have been designated by the second-cache control unitA.

Growing community of inventors

Kawasaki, Japan

Mie Tonosaki