Kabushiki Kaisha Toshiba

Micron Technology Incorporated

Midori Morooka

Tomoharu Tanaka

Koichi Fukuda

Hiroyuki Dohmae

Takahiko Hara

Apparatuses are described that include stacked arrays of memory cell strings and their methods of operation. Apparatuses include architectures that reduce the use of several common components, allowing greater device density and smaller device size for a given semiconductor area.

Architecture for 3-D NAND memory

A semiconductor device includes a plurality of semiconductor chips and a memory device. The semiconductor chips are provided in a package. Each of the semiconductor chips includes a memory cell array having memory cells which stores data, an output buffer which outputs data read from the memory cell array to an exterior of the semiconductor chip and a control circuit which controls driving power of the output buffer. The memory device stores the number of semiconductor chips provided in the package. The control circuit controls the driving power according to the number of semiconductor chips stored in the memory device.

Memory circuit system having semiconductor devices and a memory

The present invention discloses a semiconductor integrated circuit device having nonvolatile semiconductor memory cells, bit lines each connected to one end of the nonvolatile semiconductor memory cells, and a data circuit connected to the bit lines to temporarily store program data for the nonvolatile semiconductor memory cells. During a data write operation, the data circuit changes a potential transferred to each bit line in accordance with a program order of the program data.

Semiconductor integrated circuit device wherein during data write a potential transferred to each bit line is changed in accordance with program order of program data

A semiconductor memory device includes: a memory cell array; a sense amplifier circuit for reading and writing data of the memory cell array page by page; a verify-judge circuit configured to judge write or erase completion based on the verify-read data held in the sense amplifier circuit; and data latches disposed for the respective columns in the memory cell array to be attached to the verify-judge circuit, into which column separation data are written to serve for excluding the corresponding columns from a verifying object, wherein the column separation data are automatically set in the data latches in an initial set-up mode at a power-on time so that at least a part of inaccessible columns for users are excluded from the verifying object.

Semiconductor memory device

2 or more sets of initial setup data specifying different operation conditions are stored in a memory cell array comprising electrically-rewritable non-volatile memory cells arranged therein. A control circuit reads a set of initial setup data out of the 2 or more sets of initial setup data via an sense amplifier circuit based on the area information. The initial setup data is transferred to an initial setup data latch and stored therein.

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Yokohama, Japan

Midori Morooka