Sony Semiconductor Solutions Corporation

Midori Aizawa

Masami Kuroda

Haruko Takahashi

A logic simulation device according to an aspect of the present disclosure includes an operation model of a resistance-change memory element. The resistance-change memory element is provided between two terminals. The operation model includes a register section for holding data, a truth table, and a determining section. The truth table defines a relationship between signal values of the two terminals, and data writing to the register section and data reading from the register section. The determining section performs determination about the data writing and the data reading on the basis of signal values inputted to the two terminals and the truth table.

Logic simulation device

A memory system according to an aspect of the present disclosure includes a soft error generator that generates write data or read data considering a probability error by using a specific number as a random number. In the memory system, the write data or the read data considering a probability error is generated by using the random number. Herein, whether or not an error occurs is randomly changed depending on the random number. Accordingly, an error stochastically occurs, which makes it possible to reproduce a soft error.

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KANAGAWA, Japan

Midori Aizawa