Intel Corporation

Mickey L Fandrich

Virgil N Kynett

Richard J Durante

Rodney R Rozman

Geoffrey A Gould

Owen W Jungroth

Amit A Merchant

Kurt B Robinson

Jerry A Kreifels

Salim B Fedel

Timothy Wade Goodell

Neal R Mielke

Mamun Ur Rashid

Ranjeet Alexis

Steven E Wells

Sanjay S Talreja

Bharat M Pathak

Thomas C Price

Chakravarthy Yarlagadda

Keith F Underwood

William D Smith

Jerry A Kreiffels

Kelvin W Lee

Scott M Doyle

A memory device may include a controller and a plurality of flash memory dice. The controller is provided for read and write access and communications with a host. However, the controller may also be utilized to test one or more of the flash memory dice mounted on the device. In this way, testing may be achieved with a relatively modestly priced tester by making use of the capabilities of the onboard controller. As a result, the cost of a memory device may be reduced in some cases.

Apparatus and method for testing removable flash memory devices

A method and apparatus for synchronizing a micro controller in a flash memory device. An interface circuit receives a user command over a host bus. A synchronizer circuit enables an oscillator circuit if the user command specifies an operation on a flash cell array. The oscillator circuit generates a clock signal for synchronizing the micro controller. After completion of the program or erase operation, the synchronizer circuit disables the oscillator circuit if a subsequent user command that specifies another program or erase operation for the micro controller is not pending.

Synchronizing user commands to a microcontroller in a memory device

A method of queuing erase commands for a nonvolatile memory utilizes placeholder commands to prevent the depth of an operation queue from limiting the number of block erase commands that can be queued at one time. The method includes the step of storing a first erase command in the operation queue. The first erase command is designated as a placeholder erase command if no placeholder command is stored in the operation queue. Each of the first and placeholder erase commands designates at least one block of the nonvolatile memory to be erased. Each block has a corresponding status indicator. If a placeholder erase command is already stored in the operation queue, then 1) the corresponding status indicator for the block designated by the first erase command is set to indicate that the first erase command is an absorbed erase command, and 2) the first erase command is removed from the operation queue. If a program command designating the same block as any of the placeholder and absorbed erase commands is stored in the operation queue, then 1) an erase operation for the same block is performed; 2) the corresponding status indicator for the same block is cleared; and 3) the program command is executed. If the program command does not designate the same block as any of the placeholder and absorbed erase commands, then 1) the program command is executed; and 2) the program command is removed from the operation queue.

Methods for queuing and absorbing erase commands in a nonvolatile memory

An operation control method and apparatus are described. The apparatus includes a timer circuit, a blocking circuit and a control circuit. The timer circuit provides a done signal upon completion of timing a predetermined elapsed time interval initiated by a start signal. The blocking circuit receives the done signal and provides the done signal as output if the done signal is not blocked when received. The control circuit receives a begin signal indicating that the operation is to be performed and a limit signal to indicate whether or not a condition exists that would prevent the operation from being completed in a single step. If the limit signal indicates the operation can be completed in the single step, the control circuit starts the timing circuit and controls performance of the single step until the done signal is received. If the limit signal indicates the operation cannot be completed in the single step, the control circuit divides the single step into at least two sub-steps, during each sub-step, the control circuit starts the timing circuit and controls performance of the sub-step until the done signal is received. The control circuit blocks output of the done signal from the blocking circuit during each sub-step until a final sub-step. For one embodiment, the operation to be performed is an erase operation specified by a write state machine that specifies an erase block to be erased within a flash memory. Alternately, the operation to be performed is a program operation specified by a write state machine that specifies data to be programmed within a flash memory.

Controlling flash memory program and erase pulses

Circuitry for propagating test mode signals associated with a memory array including a plurality of circuits for storing test mode signals, apparatus for selectively providing test mode data to each of the circuits for storing test mode signals, and apparatus for simultaneously activating all of the circuits for storing test mode signals to provide output signals to be used for testing.

Circuitry for propagating test mode signals associated with a memory

A flash memory device having a page buffer circuit with special testing modes. The page buffer circuit comprises a plane A and a plane B, each comprising a static random access memory array. The page buffer circuit further comprises a mode control circuit that maps the plane A and the plane B as a contiguous extended memory space accessible over a host bus. The page buffer circuit also maps the plane A and the plane B as a control store for a flash array controller of the flash memory device.

Special test modes for a page buffer shared resource in a memory device

A method of prioritizing program and erase commands received in an operation queue for a memory includes the step of storing a placeholder erase command in the operation queue. Subsequent erase commands are absorbed by 1) storing the subsequent erase command in the operation queue; 2) setting a corresponding status indicator for the block designated by the subsequent erase command; and 3) removing the subsequent erase command from the operation queue, wherein the subsequent erase command becomes an absorbed erase command. If a program command that designates a same block as any one of the placeholder and absorbed erase commands is stored in the operation queue, then 1) the same block is erased; 2) the status indicator for the same block is cleared, if the same block is associated with the absorbed command; 3) the program command is executed; and 4) the program command is removed from the operation queue. If the program command does not designate a same block as any one of the placeholder and absorbed erase commands, then 1) the program command is executed; and 2) the program command is removed from the operation queue. In either case, the method then returns to continue absorbing subsequently received erase commands. This allows more erase commands to be queued for execution than what the depth of the operation queue otherwise permits.

Methods for prioritizing erase and program commands in a nonvolatile

A method of prioritizing program commands relative to erase commands in an operation queue for a memory includes the step of initiating an erase of a first block for a first erase command in the operation queue. The memory has a status indicator for each block. The status indicator indicates whether an erase command for its corresponding block has been received and removed from the operation queue but not yet executed (e.g., an absorbed erase command). An interrupt window is executed during the erasure of the first block to determine if the operation queue has received a second command for a second block. If the second command is a program command, then one of three steps is executed. If the first and second blocks are the same, then execution of the program command is deferred until after the erasure of the first block is complete. If the first and second blocks are not the same then the program command is either executed or deferred in accordance with the status indicator for the second block. If the status indicator for the second block indicates that it has been absorbed (e.g., it is set), then execution of the program command will be deferred until after the erasure of the first block is complete. Otherwise, if the status indicator for the second block indicates that it has not been absorbed (e.g. not set), then the erasure of the first block will be interrupted to execute the program command.

Method of prioritizing subsequently received program and erase commands

A flash memory device having a page buffer circuit providing a shared resource between a flash array controller circuit and a user. The page buffer circuit comprises a Plane A and a Plane B, wherein each of the planes A and B is a static random access memory array. The page buffer circuit further comprises a mode control circuit for enabling access to the planes A and B over a host bus in a user mode and access to the planes A and B by the flash array controller in a flash array controller mode.

System and method for allocating and sharingpage buffers for a flash

A memory device includes a cell array having a plurality of memory cells and a read/write circuit having circuitry for selecting, writing, and reading the memory cells according to a plurality of control signals. A control register circuit is provided that has at least one control register coupled to communicate over a central control bus. A control access circuit is provided that receives an access request targeted for the control register, and translates the access request into an access cycle on the central control bus. The access cycle loads the control register and causes the control register circuit to generate the control signals. The control access circuit receives the access request targeted for the control register from an array controller circuit that generates the access request to load the control register and generate the control signals according to a user command received over a host bus. The control register includes an address decode circuit, a function decode circuit, a master data latch, a slave data latch, and a read control circuit.

Memory device with a central control bus and a control access register

A flash memory device having a flash cell array comprising a plurality of flash cells, a flash array controller circuit for performing program and erase operations on the flash cell array according to a queue operation, and an interface circuit for generating the queue operation according to a user command and a set of command parameters received over a host bus. The interface circuit determines a set of limited resource control bits for the user command and queues the user command and associated parameters to the flash array controller circuit.

Flexible user interface circuit in a memory device

A method and device for selectively enabling and disabling write access to flash blocks in a flash memory device. A lock command locks and unlocks a flash block in a flash array containing a plurality of flash blocks. A block data row decoder selects a block data area of the flash block, and a block status row decoder selects a block status area of the flash block. A lock bit in the block status area is programmed to a first logic state if the lock command specifies a lock flash block operation, or to a second logic state if the lock command specifies a release flash block operation. If a write protect input, read from the write protect pin of the flash memory device, indicates that a write lock is enabled and if a block enabled status bit in a block status register corresponding to the block indicates that the block has the write lock, then the lock bit is read and stored into the block enabled status bit in the block status register corresponding to the block. The write protect input is read again from the write protect pin and if the write protect input indicates that the write lock is enabled, and if the block enabled status bit in the block status register corresponding to the block, as updated, indicates that the block has the write lock, then an error is signaled.

Method and device for selectively locking write access to blocks in a

Circuitry for reconfiguring a pin of an integrated circuit. The reconfiguration circuitry includes a multiplexer, whose output is coupled to the pin. Upon powering-up the integrated circuit, the multiplexer couples to the pin to a first signal that conforms to the historical definition of the pin's function. The user reconfigures the pin by issuing a command that causes the multiplexer to couple a second signal to the pin. This second signal behaves in a manner more useful to the user. The switch from the first signal to the second is achieved via a reconfiguration register, which generates the multiplexer's select signal. A control engine within the integrated circuit responds to the reconfiguration command by writing once to the reconfiguration register. The pin remains reconfigured until the integrated device is powered down.

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Placerville, CA, United States of America

Mickey L Fandrich