Kabushiki Kaisha Toshiba

Toshiba Electronic Devices & Storage Corporation

Michitomo Yamaguchi

Hiroshi Ichikawa

Tatsuo Inoue

Satoshi Kamiya

Yasuhiro Katayama

Tsukasa Kudo

Daisuke Katori

Shogo Masuda

Naoki Oshima

A control device according to an embodiment includes a first region including a CPU and a sequence signal generation circuit; and a second region including an abnormality detection circuit, a sequence signal detection circuit, a first register storing multiple methods of recovery from occurrence of abnormality, and a second register for use to select one method of recovery from the multiple methods of recovery, the second region being higher in reliability than the first region. The sequence signal generation circuit converts a first signal that specifies the one method of recovery into a sequence signal containing a second signal, which is a digital signal of a predetermined pattern, and the sequence signal detection circuit changes a set value of the second register upon receiving the second signal.

Control device and method for operating control device

A semiconductor device comprises a central processing device, a first logical circuit, and a serial memory interface circuit. The first logical circuit has a first scan chain in which a first scan pattern is set, is configured to suppress a leakage current when the first scan pattern for power saving is set in the first scan chain. The serial memory interface circuit is configured to acquire the first scan pattern for power saving from an external storage device. The leakage current of the first logical circuit is suppressed by transferring the first scan pattern for power saving acquired by the serial memory interface circuit to the first logical circuit and setting the first scan pattern for power saving in the first scan chain under control of the central processing device.

Semiconductor device and control method of semiconductor device

A data transmission device of an embodiment includes a buffer, a first determination circuit, a first flip-flop, a second flip-flop, and a second determination circuit. The buffer holds input data of a predetermined bit width. The first determination circuit determines whether or not the input data is held in the buffer. The first flip-flop receives output of the first determination circuit as input and operates at one of a rising edge and a falling edge of a second clock signal which is asynchronous with the first clock signal. The second flip-flop receives output of the first flip-flop as input and operates at another of the rising edge and the falling edge of the second clock signal. The second determination circuit determines an error based on a request signal which is synchronized with the second clock signal and output of the second flip-flop.

Data transmission device

Growing community of inventors

Kawasaki Kanagawa, Japan

Michitomo Yamaguchi