Mitsubishi Denki Kabushiki Kaisha

Michiru Hori

Masayuki Koyama

Hirohisa Machida

A viterbi decoder includes a viterbi decoding section which decodes input data, and a coding unit which codes the data decoded by the decoding unit. The number of bit error corrections in the output of the coding unit during a measurement period which is set externally are detected. Further, a synchronized state is detected based on the detected number of bit error corrections and a threshold. A threshold detecting unit detects the threshold from the detected number of bit error corrections during a threshold detection period that includes the measurement period.

Viterbi decoder and synchronism controlling method

A Trellis decoder in which a demodulated signal is handled by dividing into four areas for eight symbols, namely a pre-circuit obtains a 3-bit sign according to a high-order 4-bit sign in the demodulated signal; an area determining circuit identifies any of the four areas by obtaining a 2-bit sign in the 3-bit output from the pre-circuit; a delay circuit delays the 2-bit output from the area determining circuit and a sign for the MSB in the demodulated signal; and a selection circuit identifies a value of a high-order two bits in a received symbol according to the 2-bit output of the area determining circuit, the MSB in the demodulated signal, and an estimated value of the LSB in the received symbol outputted by a convolutional coder.

Trellis decoder

A code synchronization decision circuit of Viterbi decoder including a trigger signal generator that produces a trigger signal every time a symbol counter counts a predetermined number of symbols defined externally. A second comparator compares, in response to the trigger signal, the number of errors of symbols counted by an error counter with a threshold value that is externally set, and supplies a masking signal generator with a synchronization signal or a slip signal in response of the compared result. The masking signal generator, in response to the signals, generates a masking signal for suspending the operation of the error counter and symbol counter for a time period, during which unsuitable codes will be supplied to the code synchronization decision circuit from a re-encoder of the Viterbi decoder as one of compared values for detecting symbol errors. This makes it possible for a user to set the threshold value and the number of symbols to be counted with ease, and to implement a code synchronization decision circuit of a Viterbi decoder capable of saving power.

Code synchronization decision circuit of Viterbi decoder

In a viterbi decoding apparatus, a depuncture circuit is always synchronized with the input of a correct convolutional code irrespective of the degree of noise in the transmission path of the convolutional code. A comparator (4) makes a comparison of error numbers of slip states 1 through N stored in registers (R1) through (RN) of the register group (2), respectively, to detect a register (Rk) (k=either of 1 through N) storing the minimum error number thereby to output a minimum slip state (MINSLIP) indicating the slip state k to a slip state determination portion (5). The slip state determination portion (5) determines the minimum slip state (MINSLIP) to be a determined slip state (DSLIP) when the minimum slip state (MINSLIP) continuously indicates the same slip state M times.

Viterbi decoding apparatus, method for controlling slip state of

The configuration of a first-in first-out semiconductor storage device is simplified. A write address generating combinational circuit portion (100A) including no sequential circuits generates write addresses by using read addresses generated by a read counter portion (7).

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Tokyo, Japan

Michiru Hori