Texas Instruments Corporation

Hitachi, Ltd.

Other

Kasei Optonix, Ltd.

Michio Tanaka

Yoshitaka Tadaki

Songsu Cho

Michio Nishimura

Katsuo Yuhara

Toshihiro Sekiguchi

Keizo Kawakita

Hideo Aoki

Jun Murata

Kazuhiko Saitoh

Toshiyuki Kaeriyama

Yuji Ezaki

Shinya Nishio

Toshikazu Kumai

Hiroyuki Uchiyama

Kazuhiko Saito

Takeshi Sakai

Yujiro Suzuki

Minoru Ohtsuka

Takashi Hayakawa

Takatoshi Kakizaki

Takashi Nakamura

Katsutoshi Yamane

Takafumi Tokunaga

Norio Miura

Kiyomi Katsuyama

Keiji Shimiya

Akio Umemoto

Akihiko Konno

Masaaki Nakamura

Masayuki Yasuda

Yoshimi Torii

Tutomu Watanabe

Nobuaki Koike

Katsutoshi Matsunaga

A DRAM has, in one embodiment, a plurality of word lines each having its upper and side surfaces covered with a first insulating film, a plurality of bit lines each being provided so as to be insulated from and transverse to the word lines and being covered with a second insulating film, and a plurality of memory cells each provided at an intersection between one word line and one bit line and including a capacitor and a memory cell selection transistor, in which contact holes for connection between semiconductor regions and capacitors and between semiconductor regions and bit lines are formed in self-alignment and the second insulating film is made of a material having a permittivity smaller than that of the first insulating film.

Method of manufacturing semiconductor integrated circuit devices having a memory device with a reduced bit line stray capacity and such semiconductor integrated circuit devices

A radiographic intensifying screen set comprising a pair of a front intensifying screen and a rear intensifying screen, each comprising a support and a plurality of phosphor layers each having a binder resin and a phosphor dispersed therein, provided on the support, wherein at least some of the phosphor layers of the respective front intensifying screen and rear intensifying screen contain a fluorescent dye or a fluorescent pigment which absorbs some of emitted lights from the phosphors and emits lights having other wavelengths, the support for the front intensifying screen is a light-reflective support, and the support for the rear intensifying screen is a light-absorptive support.

Radiographic intensifying screen set

A semiconductor memory device has a semiconductor substrate, and memory cells provided at intersections between word line conductors and bit line conductors. Adjacent two memory cells for each bit line conductor form a memory cell pair unit structure, in which first semiconductor regions of the transistors of the adjacent two memory cells are united at their boundary into a single region and are connected to one of the bit line conductors via a bit line connection conductor, the gate electrodes of the transistors of the adjacent two memory cells are connected to word line conductors adjacent to each other, respectively, and the second semiconductor regions of the transistors of the adjacent two memory cells are connected to the respective information storage capacitors. A series of memory cell pair unit structures formed under one bit line conductor is positionally shifted with respect to series of memory cell pair unit structures formed under adjacent first and second bit line conductors on opposite sides of the one bit line conductor, respectively, such that a second information storage capacitor of a memory cell pair unit structure formed under the adjacent first bit line conductor and a first information storage capacitor of a memory cell pair unit structure formed under the adjacent second bit line conductor are located adjacent to a bit line connection conductor of a memory cell pair unit structure formed under the one bit line conductor.

Semiconductor integrated circuit device including a memory device having

In an embodiment of a method of manufacturing semiconductor integrated circuit devices according to the present invention, word lines are provided in a straight form, which serve as gate electrodes of two selecting MOSFETs formed symmetrical about a center portion of an active region surrounded by a LOCOS oxide film on a semiconductor substrate, and bit lines have straight segments and protruding segments. Each protruding segment is formed to protrude from the bit line and is connected through a first contact hole to a first semiconductor region formed at the center portion of the active region. The straight line segments and the protruding segments are formed separately by two separate exposure steps.

Method of manufacturing semiconductor integrated circuit devices using

A semiconductor device, such as a dynamic RAM, and method of making it. A number of stacked cell capacitors are placed at a prescribed spacing in an alignment direction on top of a p.sup.- -type silicon substrate (1). Each capacitor has a nearly perpendicular cylindrical lower electrode (cylindrical polysilicon layer (96)), a dielectric film (silicon nitride film (77)), and upper electrode (plate electrode (78) made of polysilicon). The spacing in the alignment direction is smaller than the inner diameter of the lower electrode.

Method of forming a semiconductor device have a screen stacked cell

A phase shifting mask is used for manufacturing a semiconductor integrated circuit device including a conductor pattern in which the line width of patterned conductor strips or the space between patterned conductor strips is not constant. For main transparent areas in the mask corresponding to the conductor pattern, auxiliary pattern segments are provided for compensating changes in the phase distribution of transmitted light caused by changes of the line width or the space. Alternately, the spaces between the conductor strips are adjusted to suppress the changes in the phase distribution of transmitted light. Whether the auxiliary pattern segments should have the phase shifting function is determined depending upon the disposition of the main transparent areas.

Method of manufacturing a semiconductor integrated circuit device using

A semiconductor memory device has a semiconductor substrate, word line conductors and bit line conductors, and memory cells provided at intersections between the word line conductors and bit line conductors. Adjacent two memory cells for each bit line conductor form a memory cell pair unit structure, in which first semiconductor regions of the transistors of the adjacent two memory cells are united at their boundary into a single region and are connected to one of the bit line conductors via a bit line connection conductor, the gate electrodes of the transistors of the adjacent two memory cells are connected to word line conductors adjacent to each other, respectively, the second semiconductor regions of the transistors of the adjacent two memory cells are connected to the respective information storage capacitors. A series of memory cell pair unit structures formed under one bit line conductor is positionally shifted with respect to the series of memory cell pair unit structures formed under adjacent first and second bit line conductors on opposite sides of the one bit line conductor, respectively, such that a second information storage capacitor of a memory cell pair unit structure formed under the adjacent first bit line conductor and a first information storage capacitor of a memory cell pair unit structure formed under the adjacent second bit line conductor are located adjacent to a bit line connection conductor of a memory cell pair unit structure formed under the one bit line conductor.

The etch-back amount of a silicon oxide film of a memory array which is a higher altitude portion is increased when etching back and flattening the silicon oxide film by arranging a first-layer wiring on a BPSG film covering an upper electrode of an information-storing capacitative element only in a peripheral circuit but not arranging it in the memory array. Thus, a DRAM having a stacked capacitor structure is obtained such that the level difference between the memory array and peripheral circuit is decreased, and the formation of wiring and connection holes are easy.

Method for forming semiconductor integrated circuit device having a

A DRAM has memory cells provided at crossing points between word line conductors and bit line conductors. Each memory cell has a cell selection transistor and an information storage capacitor arranged over the bit line conductors. Unit active regions are defined in a main surface of a semiconductor substrate by a field isolation pattern. The field isolation pattern has a controlled length of extension of bird's beaks so that channel formation regions in each unit active region has almost no stepped portion to provide the cell selection transistors with a stabilized threshold voltage.

Semiconductor integrated circuit device including a DRAM in which a cell

A memory device has a semiconductor substrate, and memory cells provided at intersections between word line conductors and bit line conductors. Each memory cell has a switching transistor and an information storage capacitor. Adjacent two memory cells for each bit line conductor form a memory cell pair unit structure, in which first semiconductor regions of the transistors of the adjacent two memory cells are united at their boundary into a single region and are connected to one of the bit line conductors via a bit line connection conductor, the gate electrodes of the transistors of the adjacent two memory cells are connected to word line conductors adjacent to each other, respectively, the second semiconductor regions of the transistors of the adjacent two memory cells are connected to the respective information storage capacitors. A series of memory cell pair unit structures formed under one bit line conductor is positionally shifted with respect to a series of memory cell pair unit structures formed under adjacent first and second bit line conductors on opposite sides of the one bit line conductor, respectively, such that a second information storage capacitor of a memory cell pair unit structure formed under the adjacent first bit line conductor and a first information storage capacitor of a memory cell pair unit structure formed under the adjacent second bit line conductor are located adjacent to a bit line connection conductor of a memory cell pair unit structure formed under the one bit line conductor.

This invention relates to a radiographic intensifying screen excellent in sharpness and durability, which comprises a support, a fluorescent layer formed on the support, and a protective layer formed by coating a solution containing a protective layer-forming resin on the fluorescent layer, wherein a water repellent layer or a resin layer which may optionally contain a water repellent is provided between the fluorescent layer and the protective layer, or the fluorescent layer may optionally contain a water repellent, and also relates to a process for preparing the same.

Radiographic intensifying screen and process for preparing the same

An intensifying screen having high physical durability and chemical resistance in which a curable resin is used as a resinous binder of a radioluminescent phosphor can easily be manufactured by employing an ultraviolet radiation-curable resin composition as the resinous binder. A dispersion comprising the ultraviolet radiation-curable resin composition and the radioluminescent phosphor dispersed in the composition is applied to the surface of a support to form a coating on the support, and the coating is cured by exposure to ultraviolet radiation to form a fluorescent layer on the support.

Process for manufacturing a radiographic intensifying screen

Growing community of inventors

Ome, Japan

Michio Tanaka