Hitachi-high-technologies Corporation

Michio Nakano

Takashi Hiroi

Dai Fujii

Takako Fujisawa

Shigeya Tanaka

Atsushi Ichige

Yoshiyuki Momiyama

Kazuya Hayashi

Ichiro Kawashima

Chie Shishido

Hiroshi Miyai

Taku Ninomiya

Masaaki Nojiri

Koichi Hayakawa

Shinya Murakami

Provided is a pattern inspection device for accurately simulating an electron beam image of a circuit pattern on a wafer from design data, and implementing high-precision defect detection based on the comparison between the simulated electron beam image and a real image. A pattern inspection device comprises: an image capturing unit for capturing an electron beam image of a pattern formed on a substrate; a simulated electron beam image generation unit for generating a simulated electron beam image using a parameter indicating the characteristics of the electron beam image on the basis of design data; and an inspection unit for comparing the electron beam image of the pattern, which is the image captured by the image capturing unit, and the simulated electron beam image generated by the simulated electron beam image generation unit, and inspecting the pattern on the substrate.

Pattern inspection device and pattern inspection method

A pattern inspection apparatus has a setting unit of a plurality of cell areas A and B of different cell comparison pitches and inspects the plurality of cell areas of the different cell comparison pitches in accordance with settings of the setting unit. As information to read out image data for an inspection image and a reference image from an image memory, in addition to position information of a defective image, identification information showing either a cell comparison or a die comparison and relative position information of the reference image can be set. The apparatus also has a unit for setting a plurality of inspection threshold values every inspection area and inspects a plurality of inspection areas by the plurality of inspection threshold values.

Inspection apparatus for inspecting patterns of a substrate

An image processing apparatus for wafer inspection tool that is able to perform continuously cell to cell comparison inspection, die to die comparison inspection, and cell-to-cell and die-to-die hybrid comparison inspection, employing a plurality of processors. This image processing apparatus for wafer inspection tool comprises a plurality of processors for performing parallel processing, means for cutting out image data including a forward end overlap and a rear end overlap at partition boundaries in order to cut serial data into a predetermined image size, means for distributing the cutout image data to the plurality of processors, and means for assembling results of processing performed by the plurality of processors. The forward end overlap is set greater than a pitch of the cell subject to cell to cell comparison inspection.

Image processing unit for wafer inspection tool

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Hitachinaka, Japan

Michio Nakano